System Clocking; Table 1. Speed Modes; Table 2. Common Clock Frequencies - Cirrus Logic CDB4244 Manual

4.3.1 Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudocode above for implementation details.
4.3.1.1 Map Increment (INCR)
The CS4244 has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR
is set to '0', MAP will stay constant for successive I²C reads or writes. If INCR is set to '1', MAP will auto-
increment after each byte is read or written, allowing block reads or writes of successive registers.
4.4

System Clocking

The CS4244 will operate at sampling frequencies from 30 kHz to 100 kHz. This range is divided into two
speed modes as shown in
The serial port clocking must be changed while all PDNx bits are set. If the clocking is changed otherwise,
the device will enter a mute state, see
4.4.1 Master Clock
The ratio of the MCLK frequency to the sample rate must be an integer. The FS/LRCK frequency is equal
to F , the frequency at which all of the slots of the TDM stream or channels in Left Justified or I²S formats
S
are clocked into or out of the device. The
to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode.
trates several standard audio sample rates and the required MCLK and FS/LRCK frequencies.
The CS4244 has an internal fixed ratio PLL. This PLL is activated when the
"Clock & SP Sel." register
these two modes, the PLL will activate to adjust the frequency of the incoming MCLK to ensure that the
internal state machines operate at a nominal 24.576 MHz rate. As is shown in the
sumption table, activation of the PLL will increase the power consumption of the CS4244.
FS/LRCK (kHz)
32
44.1
48
64
88.2
96
Mode
Note:
34. 128x and 192x ratios valid only in Left Justified or I²S formats.
DS900PP2
Table 1.
Mode Sampling Frequency
Single-Speed
Double-Speed

Table 1. Speed Modes

Section 4.8 on page
Speed Mode
are set to either 000 or 001, corresponding to 256x or 384x. When in either of
128x 192x
(Note 34) (Note 34)
- -
- -
- -
8.1920 12.2880
11.2896 16.9344
12.2880 18.4320
DSM

Table 2. Common Clock Frequencies

30-50 kHz
60-100 kHz
43.
and Master Clock Rate
"MCLK RATE[2:0]" bits in the
MCLK (MHz)
256x
8.1920 12.2880
11.2896 16.9344
12.2880 18.4320
16.3840
22.5792
24.5760
CS4244
bits configure the device
Table 2 illus-
Typical Current Con-
384x 512x
16.3840
22.5792
24.5760
- -
- -
- -
SSM
26