Figure 24. Single-Ended To Differential Active Input Filter; Figure 25. Single-Ended To Differential Active Input Filter - Dc Coupled Input Signal (Va/2 Centered) - Cirrus Logic CDB4244 Manual

100 k
4.6.2.3 ADC HPF
The ADC path contains an optional HPF which can be enabled or disabled for all four ADCs via the
ABLE HPF" bit in the "ADC Control 1"
of the input signal needs to be preserved in the digital output data. The HPF characteristics are given in
the ADC Digital Filter Characteristics
bles on pages
Note: If the internal bias is enabled (ADC CMx bits = '1'), the ADC HPF must be enabled to achieve full
specified performance.
The following figure shows how the recommended single-ended to differential active input filter
(Figure 24) can be modified to allow for DC coupled inputs when the HPF is disabled. Note that the volt-
age swing should not exceed the ADC full-scale input specification.
100 k

Figure 25. Single-Ended to Differential Active Input Filter - DC Coupled Input Signal (VA/2 Centered)

DS900PP2
470 pF
C0G
-
22 F
+
VA
100 k
100 k
0.01 F 22 F
100 k

Figure 24. Single-Ended to Differential Active Input Filter

register. The HPF should only be disabled when the DC component
table and plotted in
11 and 12 specify the DC offset error when the HPF is enabled or disabled.
470 pF
C0G
-
+
VA
100 k
0.01 F 22 F
100 k
634 
* Place close to AINx pins
91 
634 
634 
470 pF
C0G
91 
-
+
Section
634 
* Place close to AINx pins
91 
634 
634 
470 pF
C0G
91 
-
+
ADC1-4
AINx+
2700 pF
*
C0G
AINx-
7. The Analog Input Characteristics ta-
ADC1-4
AINx+
2700 pF
*
C0G
AINx-
CS4244
"EN-
36