Switching Specifications - Control Port; Figure 8. I²C Control Port Timing - Cirrus Logic CDB4244 Manual

SWITCHING SPECIFICATIONS - CONTROL PORT

Test conditions (unless otherwise specified): Inputs: Logic 0 = GND = 0 V, Logic 1 = VL; SDA load capacitance equal to maxi-
mum value of C specified below
b
SCL Clock Frequency
RESET Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Input Hold Time from SCL Falling
SDA Output Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
SDA Bus Load Capacitance
SDA Pull-Up Resistance
Notes:
31. All specifications are valid for the signals at the pins of the CS4244 with the specified load capacitance.
32. 2 ms + (3000/MCLK). See
33. Data must be held for sufficient time to bridge the transition time, t
RST
t irs
Stop
SDA
t buf
SCL
DS900PP2
(Note 31).
Parameters
Section 4.2.1.
Start
t high
t hdst
t t
low hdd
Figure 8. I²C Control Port Timing
Symbol
f
scl
t
irs
t
buf
t
hdst
t
low
t
high
t
sust
(Note 33) t
hddi
t
hddo
t
sud
t
r
t
f
t
susp
C
b
R
p
, of SCL.
f
Repeated
Start
t
hdst
t sud t sust
CS4244
Min Max
- 550
(Note 32) -
1.3 -
0.6 -
1.3 -
0.6 -
0.6 -
0 0.9
0.2 0.9
100 -
- 300
- 300
0.6 -
- 400
500 -
Stop
t f
t susp
t r
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
pF

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