Applications; Recommended Power-Up Sequence; System Clocking; Master Clock - Cirrus Logic CS4265 Manual

4. APPLICATIONS

4.1

Recommended Power-Up Sequence

1. Hold RESET low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is
reset to its default settings.
2. Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The con-
trol port will be accessible.
3. The desired register settings can be loaded while the PDN bit remains set.
4. Clear the PDN bit to initiate the power-up sequence.
4.2

System Clocking

The CS4265 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three
speed modes as shown in
4.2.1

Master Clock

MCLK/LRCK must maintain an integer ratio as shown in
frequency at which audio samples for each channel are clocked into or out of the device. The FM bits (See
"Functional Mode (Bits 7:6)" on page
on page 39.) configure the device to generate the proper clocks in Master Mode, and receive the proper
clocks in Slave Mode.
LRCK frequencies.
LRCK
(kHz)
64x
32 -
44.1 -
48 -
64 -
88.2 -
96 -
128 8.1920 12.2880
176.4 11.2896 16.9344
192 12.2880 18.4320
Mode
24
Table 1.
Mode
Single-Speed
Double-Speed
Quad-Speed

Table 1. Speed Modes

38.) and the MCLK Freq bits (See
Table 2 illustrates several standard audio sample rates and the required MCLK and
96x 128x 192x
- -
- -
- -
- 8.1920 12.2880
- 11.2896 16.9344
- 12.2880 18.4320
16.3840 24.5760
22.5792 33.8680
24.5760 36.8640
QSM

Table 2. Common Clock Frequencies

Sampling Frequency
4-50 kHz
50-100 kHz
100-200 kHz
Table 2. The LRCK frequency is equal to Fs, the
MCLK (MHz)
256x 384x
- 8.1920 12.2880
- 11.2896 16.9344
- 12.2880 18.4320
16.3840 24.5760
22.5792 33.8680
24.5760 36.8640
32.7680 -
45.1584 -
49.1520 -
"MCLK Frequency - Address 05h"
512x 768x
16.3840 24.5760
22.5792 33.8680
24.5760 36.8640
32.7680 -
45.1584 -
49.1520 -
- -
- -
- -
DSM SSM
CS4265
1024x
32.7680
45.1584
49.1520
-
-
-
-
-
-
DS657F3