Serial Port Data Select (Address 09H) - Cirrus Logic CDB4244 Manual

6.5.3 Serial Data Output Sidechain
Setting this bit enables the SDOUT1 side chain feature. In this mode, the samples from multiple devices
can be coded into one TDM stream. See
SDO CHAIN
0
1
6.5.4 Master / Slave
Setting this bit places the CS4244 in master mode, clearing it places it in slave.
MASTER / SLAVE CS4244 is in:
0
1
Note: I²S and Left Justified are the only serial port formats that are available if the CS4244 is placed
into Master Mode.
6.6

Serial Port Data Select (Address 09h)

7 6
ADC34 CM ADC12 CM
6.6.1 ADCx Common Mode
Enables the ADCx input pin bias to VQ. ADC1 and ADC2 are controlled together; ADC3 and ADC4 are
controlled together. See
Note: If these bits are set to '1', the ADC HPF must be enabled to achieve full specified performance.
ADCx CM
0
1
6.6.2 DAC1-4 Data Source
Sets which portion of data is to be routed to the DAC1-4 data paths.
DAC1-4 SOURCE Data is routed into the DAC1-4 path from:
000
001
010
011
100
101
110
111
DS900PP2
Sidechain is:
Disabled
Enabled
Slave Mode
Master Mode
5 4
DAC1-4 SOURCE[2:0]
Section 4.6.2.1 Analog Inputs
AINx+ and AINx- bias to VQ is:
Disabled
Enabled
Slots 1-4 of the TDM stream on SDIN1
Slots 5-8 of the TDM stream on SDIN1
Slots 9-12 of the TDM stream on SDIN1
Slots 13-16 of the TDM stream on SDIN1
Slots 1-4 of the TDM stream on SDIN2
Slots 5-8 of the TDM stream on SDIN2
Slots 9-12 of the TDM stream on SDIN2
Slots 13-16 of the TDM stream on SDIN2
Section 4.6.2 ADC Path for more details.
3
for more details.
2 1
Reserved[2:0]
CS4244
0
51