Analog Input Convert Clock Signal Behavior - Advantech iDAQ-900 Series User Manual

The start and stop of acquisition can also be delayed in number of samples after
receiving the corresponding trigger signal. As shown in Figure 3.7, the start of acqui-
sition is delayed by 3 samples after receiving a start trigger, and the stop of acquisi-
tion is delayed by 2 samples after receiving a stop trigger.
Figure 3.7 Start and stop of the analog input acquisition with delay
Refer to section 3.1.1 Trigger and Signal Routing for possible signal routings and
configurations for these timing signals (start trigger, stop trigger, and sample clock).
Buffered analog input acquisition has several advantages over instant analog input
acquisition:
The start and stop time of acquisition (or duration of the acquisition) can be pre-

cisely controlled by hardware trigger signals.
ADC conversion rate is configurable, and the sample rate can be much higher

by using hardware sample clock signal.
Time between samples is deterministic.

3.3.3

Analog Input Convert Clock Signal Behavior

While the frequency of the sample clock can be configured as a deterministic value,
the convert clock of the ADC may present different behaviors in different types of
analog input modules.
Multiplexed Analog Input Module
In a multiplexed analog input module, there is only one ADC performing conversion,
which means only one channel at a time can be converted. An analog multiplexer
(MUX) in front of the ADC routes the analog input channel to be converted to the
ADC input as shown in Figure 3.8. Because the conversion time of the ADC remains
the same, the maximum convert rate of the ADC will be shared by all enabled analog
input channels. That is, if more analog input channels are enabled, the maximum
allowable convert rate for each channel becomes smaller.
Figure 3.8 Multiplexed analog input module block diagram
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