Advantech iDAQ-900 Series User Manual page 41

The start and stop of the acquisition are controlled by the start trigger and stop trig-
ger, respectively. When configuration is completed, the acquisition engine of the
iDAQ chassis is at standby state. After receiving a start trigger, acquisition becomes
active and each rising edge of the sample clock acquires one analog input sample.
The acquisition active period lasts until a stop trigger is received, which ends the
acquisition. This is shown in Figure 3.28.
Figure 3.28 Start and stop of the digital input acquisition
The start and stop of acquisition can also be delayed in number of samples after
receiving the corresponding trigger signal. As shown in Figure 3.29, the start of
acquisition is delayed by 3 samples after receiving a start trigger, and the stop of
acquisition is delayed by 2 samples after receiving a stop trigger.
Figure 3.29 Start and stop of the digital input acquisition with delay
Refer to 3.1.1 Signal Routing for possible signal routings and configurations for these
timing signals (start trigger, stop trigger, and sample clock).
Buffered digital input acquisition has several advantages over instant digital input
acquisition:
The start and stop time of acquisition (or duration of the acquisition) can be pre-

cisely controlled by hardware trigger signals.
Sample rate can be much higher by using hardware sample clock signal.

Time between samples is deterministic.
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