Advantech iDAQ-900 Series User Manual page 31

When the sample clock rises, the multiplexed analog input module automatically gen-
erates required convert clocks using the maximum allowable convert clock rate of the
ADC for all enabled channels. The MUX routes one of the enabled channels for each
convert clock in the order of channel number. Figure 3.9 shows an example when 3
analog input channels (0, 1, and 2) are enabled. By this acquisition method, the tim-
ing of conversion for all enabled channels can be as close as possible, which
approaches the result of a simultaneously sampled analog input module.
Figure 3.9 Acquisition of a multiplexed analog input module
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