AD8333-EVALZ
Current Summing
The output transimpedance amplifiers, A1 through A4, are
configured as I-to-V converters to convert the output current of
the AD8333 to a voltage. The low-pass filters formed by the
feedback components are designed for single-channel operation
with ±5 V supplies.
Optional R4 and R5 resistors are provided to sum the two
channels. When R4 and R5 are installed, R2 and R3 are
removed and the sum of the outputs is seen at the I1 and Q1
output SMA connectors. If large signal levels are expected, the
feedback resistor and capacitor values, 787 Ω and 2.2 nF, can be
halved and doubled, respectively, to optimize the output swing.
The filter capacitor values can be changed if other frequencies
are desired.
Reset Input
For normal operation, the reset input is high (no reset). To drive
the reset with a dynamic signal, provision is made to connect a
signal generator at the RST input. A 49.9 Ω, 0603 surface-
mount resistor can be installed at R15 to terminate the reset
input for pulsed experiments. In this configuration, the jumper
at RST is not used and must be removed to avoid loading the
power supply.
CH 1 RF INPUT
CH 2 RF INPUT
MEASUREMENT SETUP
Figure 2 displays the connector and user-selectable jumper
locations. A typical board and test equipment setup is shown in
Figure 4. Two signal generators, a power splitter, and a ±5 V,
300 mA (minimum) power supply are required. Synchronize
the signal generators for optimum results. Remember that the
f
4LO
frequency of the RF source. For example, to detect signals with
a nominal center frequency of 5 MHz, an f
is applied to the oscillator input. For an applied RF signal of
5.01 MHz, the mix frequencies are 10 kHz and 10.01 MHz.
Because of the low-pass active filter of the transconductance
amplifiers (A1 through A4), 10 kHz is observed at the output.
Take care to avoid over driving the LNA input of the AD8332.
The LNA gain is 19 dB (9.5×) and the maximum output swing
must not be exceeded; −10 dBm suffices for many experiments.
The f
ideal interface to the AD8333.
The f
sheet for minimum signal levels, then adjust the signal generator
output level accordingly.
f
INPUT
4LO
CHANNEL 1
PHASE BITS
CHANNEL 2
PHASE BITS
Figure 2. Evaluation Board Layout
Rev. B | Page 4 of 12
signal generator frequency is four times that of the nominal
input is ac-coupled to a 5 V LVDS buffer to provide an
4LO
level is frequency dependent; consult the
4LO
+5V, GND, –5V
ENABLE
CH 1 I OUTPUT
CH 1 Q OUTPUT
CH 2 I OUTPUT
CH 2 Q OUTPUT
RESET
frequency of 20 MHz
4LO
AD8333
data
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