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*1 Although the wide operating character range is guaranteed, a quick and excessive voltage variation may not be
guaranteed during access by the MPU. The low-voltage data hold characteristics are valid during Sleep mode. No
access by the MPU is allowed during this time.
*2 D0 to D5, D6 (SCL), D7 (SI), A0, RES, XCS, XWR (E), PS, IF, C86
*3 The resistance if a 0.1-volt voltage is supplied between the SEGn, SEGSn, COMn or COMSn output pin and each
power pin (V
, V
, V
or V
1
2
3
R
= 0.1V/∆I
ON
where, ∆I is current that flows when the 0.1-volt voltage is supplied between the power supply and output.
*4 Applied if not accessed by the MPU during character display and if the built-in power circuit and oscillator are
operating.
Display character:
*5 Current consumption if always written in "fcyc". The current consumption during access is roughly proportional to
the access frequency (fcyc).
t
*6 The "
" (reset time) indicates a time period from the rising edge of RES signal to the completion of internal circuit
R
reset. Therefore, the SED1225 enters the normal operation status after "
*7 Defines the minimum pulse width of RES signal. A pulse width greater than "
RES
*8 The following provides the relationship between the oscillator frequency (f
frame frequency (f
).
FR
= 13 × 26 × f
f
(3-line display)
OSC
FR
= 13 × 18 × f
(2-line display)
FR
<Reference>
= (1/128) × f
f
BLK
*9 Enter the waveforms in 40% to 60% duty to use an external clock instead of the built-in oscillator. If no external clock
is entered, fix it to high. (Normal high)
). It is defined within power voltage (2).
4
V
DD
–2.4
V
V
SS
V
DD
V
SS
All signal timings are based on 20% and 80% of Vss.
FR
EPSON
t
".
R
t
t
RES
t
t
RW
R
) for built-in circuit driving and the
OSC
SED1225 Series
" must be entered for reset.
RW
3–27
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