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SED1225 Series
(3) Serial interface
XCS
A0
SCL
SI
Item
System clock cycle
SCL "Hi" pulse width
SCL "Lo" pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-to-SCL time
Item
System clock cycle
SCL "Hi" pulse width
SCL "Lo" pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-to-SCL time
*1 The input signal rise and fall times (
3–30
t
CSS
t
SAS
t
SCYC
t
SLW
t
SDS
Signal
Symbol
t
SCYC
t
SCL
SHW
t
SLW
t
SAS
A0
All timing must be based on
t
SAH
20% and 80% of V
t
SDS
SI
t
SDH
t
CSS
XCS
t
CSH
Signal
Symbol
t
SCYC
t
SCL
SHW
t
SLW
t
SAS
A0
All timing must be based on
t
SDH
20% and 80% of V
t
SDS
SI
t
SDH
t
CSS
XCS
t
CSH
t
t
r,
f) are defined to be 25 nsec max (except for RES input).
t
r
V
x 0.8 [V]
SS
V
x 0.2 [V]
SS
EPSON
t
CSH
t
SAH
t
SHW
t
SDH
(Ta = –30 to +85°C, V
SS
Conditions
Min.
3000
2850
150
50
800
.
SS
50
50
400
2500
(Ta = –30 to +85°C, V
SS
Conditions
Min.
1400
1300
50
50
500
.
SS
30
30
200
1500
t
f
= –3.6V to –1.7V)
Max.
Unit
—
—
ns
—
—
ns
—
—
ns
—
—
ns
—
= –3.3V to –2.7V)
Max.
Unit
—
—
ns
—
—
ns
—
—
ns
—
—
ns
—
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