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3-37
Protection Functions
Auto reclosing
The start signal of any Iϕ> stage initiating auto reclosing (AR) can
be used to block the I
> stage to avoid the I
> stage with a long
0T
0T
intermittent setting to interfere with the AR cycle in the middle of
discrimination time.
Usually the I
> stage itself is not used to initiate any AR. For
0T
transient faults the AR will not help, because the fault phenomena
itself already includes repeating self extinguishing.
Intermittent time
Single transient faults make the protection to pick up, but will not
cause trip if the stage has time to release between to successive
faults. When starting happens often enough, such intermittent faults
can be cleared using the intermittent time setting.
When a new fault happens within the set intermittent time, the
operation delay counter is not cleared between adjacent faults and
finally the stage will trip. A single transient fault is enough to start
the stage and increase the delay counter by 20 ms. For example if the
operating time is 140 ms, and the time between two peaks does not
exceed the intermittent time setting, then the seventh peak will cause
a trip (Figure 3.22).
Operation time setting and the actual operation time
When the algorithm detects the direction of the fault outwards from
the bus, the stage picks up and the operation delay counter is
incremented with 20 ms and a start signal is issued. If the time
between successive faults is less than 40 ms, a trip signal is issued
when the operation time is full.
When the time between successive faults is more than 40 ms, the
stage will release between the faults and the delay counting is
restarted from zero for every single fault and no trip will be issued.
For such cases the intermittent setting can be used. Figure 3.21
shows an example of how the intermittent setting works. The upper
start and trip signals are a case with zero intermittent setting. The
lower signals are another case with intermittent setting 0.12 s. The
operation time setting is 0.14 s in both cases corresponding to seven
20 ms time slots with faults.
The time between the second and the third fault exceeds the release
time + intermittent time. Thus the operation delay counter is cleared
in both cases: with zero intermittent time and with 0.12 s intermittent
time.
857-UM001A-EN-P – July 2009
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