Supermicro SYS-521C-NR User Manual page 18

#0 #0 #0 #0
E
#1 #1 #1 #1
F
G
H
PCIe 5.0 x16
LUIO2
PCIe 5.0 x8
JAIOM1
LANE REVERSAL
PCIe 5.0 x8
MCIO x8
JPCIE1 LANE REVERSAL
PCIe 5.0 x4
MCIO x4
JNVME1
PCIe 5.0 x4
MCIO x4
JNVME2
PCIe 5.0 x4
MCIO x4
JNVME3
PCIe 5.0 x4
MCIO x4
JNVME4
USB3.0 x2
Rear
JUSBRJ45
USB2.0 x2
Header
JUSB1
JAIOM1
JAIOM2
JFP2
SlimSAS LP
x8
JS1
SlimSAS LP
x4
JS2
Note: This is a general block diagram and may not exactly represent the features on your
motherboard. See the System Specifications appendix for the actual specifications of your
motherboard.
#0
A
#1
B
CPU
PCIe 5.0 x16
PE1[0-15] PE0[0-15]
LANE REVERSAL
PE2[8-15]
PCIe 5.0 x4
PE2[0-7] PE4[0-3]
JNVME5
PCIe 5.0 x4
PE4[4-7]
JNVME6
PE3[0-3]
PCIe 5.0 x4
PE4[8-11]
JNVME7
PE3[4-7]
PCIe 5.0 x4
PE4[12-15]
JNVME8
PE3[8-11]
PE3[12-15]
DMI
MAC4
PCH
USB3[6:7] USB2[4:5]
USB2[0:1] PCIe3[4]
ESPI
TPM
USB2[2:3] SPI1
SPI
USB2[6]
USB2[7]
MUX
USB2[8:9]
BIOS BOOT FLASH
SATA3[8:15]
SATA3[16:19]
PCIe3.0 x2
PCIe3[0-1]
PCIe3.0 x2
PCIe3[2-3]
Figure 1-6. System Block Diagram
18
#0 #0 #0
#1 #1 #1
C
D
RUIO2
MCIO x4
MCIO x4
MCIO x4
MCIO x4
NCSI
MUX
NCSI
SW
PCIe 5.0 x8
JAIOM1_1
eMMC
MAC3 eMMC
VGA
Upgrade connector
COM1
BMC
AST2600
PHY
MAC1
RTL8211F
SPI2 I2C FWSPI
BMC BOOT FLASH
TPM
MUX
CPLD BOOT FLASH
PCIe x2 M.2 M-Key
PCIe x2 M.2 M-Key
Chapter 1: Introduction
Upgrade connector
MCIO x8
JAIOM2_2
JNCSI1
PCIe 5.0 x8
JAIOM2
JAIOM1
PCIe 5.0 x8
JAIOM2_1
MCIO x8 MCIO x8
Upgrade connector
IPMI LAN IPMI LAN
RTL8211F RJ45
JUSBRJ45
CPLD