Table 6-3. Jetson Tx2 Nx Usb 3.0 And Pcie Lane Mapping Configurations - Nvidia Jetson TX2 NX Manual

Jetson TX2 NX
Pin # Module Pin Name
Function
148 PCIE0_TX2_N RSVD
150 PCIE0_TX2_P RSVD
154 PCIE0_TX3_N RSVD
156 PCIE0_TX3_P RSVD
160 PCIE0_CLK_N PCIE0_CLK_N
162 PCIE0_CLK_P PCIE0_CLK_P
180 PCIE0_CLKREQ* PCIE0_CLKREQ*
(PCIE1_RX0_N)
167 PCIE1_RX0_N
RSVD
(PCIE1_RX0_P)
169 PCIE1_RX0_P
RSVD
(PCIE1_TX0_N)
172 PCIE1_TX0_N
RSVD
(PCIE1_TX0_P)
174 PCIE1_TX0_P
RSVD
(PCIE1_CLK_N)
173 PCIE1_CLK_N
RSVD
(PCIE1_CLK_P)
175 PCIE1_CLK_P
RSVD
(PCIE1_CLKREQ*)
182 PCIE1_CLKREQ*
RSVD
183 (PCIE1_RST*) RSVD PCIE1_RST*
161 USBSS_RX_N USBSS_RX_N
163 USBSS_RX_P USBSS_RX_P
166 USBSS_TX_N USBSS_TX_N
168 USBSS_TX_P USBSS_TX_P
Notes: In the Type/Dir column, Output is from Jetson TX2 NX. Input is to Jetson TX2 NX. Bidir is for Bidirectional signals.
Table 6-3 lists the mapping options for Jetson TX2 NX.
Table 6-3. Jetson TX2 NX USB 3.0 and PCIe Lane Mapping Configurations
Module Pin Names
Tegra X2 Lanes
USB 3.0 PCIe
1 1x1 + 1x2
Usage on DevKit Carrier
Board
NVIDIA Jetson TX2 NX
Tegra X2 Signal Usage/Description
− Reserved
− Reserved
− Reserved
− Reserved
PEX_CLK1N
PCIe #0 Reference Clock (PCIe
Ctrl #0)
PEX_CLK1P
PCIE #0 Clock Request (PCIe
PEX_L0_
Ctrl #0). 47kΩ pull-up to 3.3V
CLKREQ_N
on the module.
PCIe 1 Receive 0– (PCIe Ctrl #2
PEX_RX0N
Lane 0)
PCIe 1 Receive 0+ (PCIe Ctrl #2
PEX_RX0P
Lane 0)
PCIe 1 Transmit 0– (PCIe Ctrl
PEX_TX0N
#2 Lane 0)
PCIe 1 Transmit 0+ (PCIe Ctrl
PEX_TX0P
#2 Lane 0)
PCIe 1 Reference Clock– (PCIe
PEX_CLK3N
Ctrl #2)
PCIe 1 Reference Clock+ (PCIe
PEX_CLK3P
Ctrl #2)
PCIE 1 Clock Request (PCIe
PEX_L2_
Ctrl #2). 47kΩ pull-up to 3.3V
CLKREQ_N
on the module.
PCIe 1 Reset (PCIe Ctrl #2).
PEX_L2_RST_N 4.7kΩ pull-up to 3.3V on the
module.
PEX_RX1N
USB SS Receive (USB 3.0 Ctrl
#1)
PEX_RX1P
PEX_TX1N
USB SS Transmit (USB 3.0 Ctrl
#1)
PEX_TX1P
PCIE1 PCIE0_1
Lane 0 Lane 2
PCIe#2_0 PCIe#0_1
M.2 Key E M.2 Key M
Usage on DevKit
Carrier Board
M.2 Key M
M.2 Key M
M.2 Key M
M.2 Key M
M.2 Key M
M.2 Key E
USB Hub
PCIE0_0 USBSS
Lane 4 Lane 1
PCIe#0_0 USB_SS#1
USB Hub
DG-10141-001_v1.1 | 17
USB and PCI Express
Direction Pin Type
− −
− −
− −
− −
PCIe PHY
Bidir Open Drain 3.3V
Input
PCIe PHY
Input
PCIe PHY
Output
PCIe PHY
Input
Open Drain 3.3V
Output
Input USB SS PHY
Output USB SS PHY