Edp And Dp Routing Guidelines; Figure 7-2. Dp And Edp Connection Example On Dp0 Pins; Figure 7-3. Edp Differential Main Link Topology - Nvidia Jetson TX2 NX Manual

Figure 7-2. DP and eDP Connection Example on DP0 Pins
Jetson
Tegra
DP
DPx_HPD
DP_AUX_CHx_HPD
DPx_AUX_N
DP_AUX_CHx_N
DPx_AUX_P
DP_AUX_CHx_P
eDP
DPx_TXD3_N
HDMI_DPx_TXDN3
DPx_TXD3_P
HDMI_DPx_TXDP3
DPx_TXD2_N
HDMI_DPx_TXDN2
DPx_TXD2_P
HDMI_DPx_TXDP2
DPx_TXD1_N
HDMI_DPx_TXDN1
DPx_TXD1_P
HDMI_DPx_TXDP1
DPx_TXD0_N
HDMI_DPx_TXDN0
DPx_TXD0_P
HDMI_DPx_TXDP0
Notes:
Level shifter required on DPx_HPD to avoid the pin from being driven when Jetson TX2 NX is
•
off. The level shifter must be non-inverting (preserve the polarity of the HPD signal from the
display). The reference design uses a BJT level shifter and a resistor divider is needed. See the
reference design if a similar approach will be used.
Load Switch enable is from powergood pin of main 3.3V supply.
•
7.2.1.1

eDP and DP Routing Guidelines

Figure 7-3 shows the eDP/DP topology, and Table 7-7 provides the eDP and DP signal routing
requirements.
Figure 7-3. eDP Differential Main Link Topology
Jetson
Tegra
P
DP
Pkg
Driver
N
NVIDIA Jetson TX2 NX
VDD_3V3_SYS
VDD_1V8
3V3_IO_PG
Level Shifter
0 / 1
88/96 1.8V 3.3V
0.1uF
90/98
92/100
0.1uF
0.1uF
57/81
59/83
0.1uF
0.1uF
51/75
53/77
0.1uF
0.1uF
45/69
47/71
0.1uF
0.1uF
39/63
41/65
0.1uF
Common Mode
Chokes & ESD
eDP
Conn
VDD_3V3_EDP
Load Switch
IN OUT
EN
10kΩ
VDD_3V3_SYS
TPD4E 05U06
DG-10141-001_v1.1 | 34
Display
DP
Conn
.
PWR
20
PWR_RET
19
HPD
18
AUXN
17
GND
16
AUXP
15
CEC_DP
14
MODE
13
LANE_3N
12
GND
11
LANE_3P
10
LANE_2N
9
GND
8
LANE_2P
7
LANE_1N
6
GND
5
LANE_1P
4
LANE_0N
3
GND
2
LANE_0P
1