Spi Design Guidelines; Figure 11-3. Basic Spi Master And Slave Connections; Figure 11-4. Spi Topologies - Nvidia Jetson TX2 NX Manual

Figure 11-3 shows the basic connections used.
Figure 11-3. Basic SPI Master and Slave Connections
Jetson Master
SPIn_CSx
SPIn_SCK
SPIn_MOSI
SPIn_MISO
11.2.1

SPI Design Guidelines

Figure 11-4 shows the SPI topologies and Table 11-5 gives the SPI interface signal routing
requirements.
Figure 11-4. SPI Topologies
Point-Point Topology
Jetson
SPI
Tegra
Device
Main trunk
Table 11-5. SPI Interface Signal Routing Requirements
Parameter
Max frequency
Configuration / device organization
Max loading (total of all loads)
Reference plane
Breakout region impedance
Max PCB breakout delay
Trace impedance
Via proximity (signal to reference)
Trace spacing (Microstrip / Stripline)
Max trace length/delay (PCB main trunk) for MOSI,
MISO, SCK and CS 2x-load star/daisy
Point-point
Max trace length/delay (Branch-A) for MOSI, MISO,
SCK and CS
2x-load star/daisy
Max trace length/delay skew from MOSI, MISO and
CS to SCK
Note: Up to four signal vias can share a single GND return via.
NVIDIA Jetson TX2 NX
SPI Slave Device
CS (Chip Select)
CLK (Clock)
MOSI (Master out, Slave in)
MISO (Master in, Slave out)
2x-Load Star Topology
Jetson
Branch-A
Tegra
Main trunk
Branch-B
Requirement
65
4
15
GND
Minimum width
and spacing
75
50 – 60
< 3.8 (24)
4x / 3x
195 (1228)
120 (756)
75 (472)
16 (100)
Jetson Slave
SPIn_CSx CS (Chip Select)
SPIn_SCK CLK (Clock)
SPIn_MOSI MOSI (Master out, Slave in)
SPIn_MISO MISO (Master in, Slave out)
SPI
Device
#1
Jetson
SPI
Tegra
Device
#2
Units
MHz
load
pF
ps
Ω
mm (ps)
dielectric
mm (ps)
mm (ps)
mm (ps)
Miscellaneous Interfaces
SPI Master Device
2x-Load Daisy Topology
SPI
Device
Branch-A #1
Main trunk Branch-B
Notes
±15%
See note
At any point
DG-10141-001_v1.1 | 61
SPI
Device
#2