Video Bios Cacheable; Delayed Transaction - Multitech IPC-623C User Manual

Award BIOS Setup

Video BIOS Cacheable

Select Enabled allows caching of the video BIOS ROM at
C0000h-F7FFFh, resulting in better video performance.
However, if any program writes to this memory area, a system
error may result.
Video RAM Cachable
Select Enabled allows caching of the video RAM, resulting in
better system performance. However, if any program writes to
this memory area, a system error may result.
8 Bit I/O Recovery Time
The recovery time is the length of time, measured in CPU
clocks, which the system will delay after the completion of any
Input/output request. This delay takes place because the CPU
is operating so much faster than the input/output bus that the
CPU must be delayed to allow for the completion of the I/O.
This item allows you to determine the recovery time allowed for
8bit I/O.
16 Bit I/O Recovery Time
This item allows you to determine the recovery time allowed for
16bit I/O. Choices from NA, 1 to 4 CPU clocks.
Memory Hole at 15M-16M
In order to improve performance, certain space in memory can
be reserved for ISA cards. This memory must be mapped into
the memory space below 16Mb.
Passive Release
When enabled, CPU to PCI bus accesses are allowed during
passive release. Otherwise, the arbiter only accepts another
PCI master access to local DRAM.

Delayed Transaction

The chipset has an embedded 32-bit posted write buffer to
support delay transactions cycles. Selected Enabled to support
compliance with PCI specification version 2.1.
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CommPlete Series 4000 Server SBC, Model IPC-623C