Measuring Power - Altera Cyclone III FPGA Starter Kit User Manual

Measuring Power

Table 4–3. LEDs Power State (Resources)
Displays
Resources
Measuring
Power
f
4–2
Cyclone III FPGA Starter Kit User Guide
LEDs
MSB LSB
LED4 LED3
The design used for power measurement is a replicated set of randomly
filled ROMs that feed a multiplier block and a shift register that is fed by
a signal that changes every clock cycle. The states shown in
and 4–3 represent the percent of the full design used. As compiled, this
full design uses:
■
Logic elements: 22,493/24,624 (91%)
■
Combinational functions: 1,961/24,624 (8%)
■
Dedicated logic registers: 21,133/24,624 (86%)
■
Total registers: 21,133
■
Total pins: 73/216 (34%)
■
Total memory bits: 524,288/608,256 (86%)
■
Embedded Multiplier 9-bit elements: 128/132 (97 %)
■
Total PLLs: 1/4 (25%)
The design example can be located by default in <kit
install>\Examples\CIII_Power_Demo. Configure the FPGA with the
SOF found in the directory.
1
The input clock (i_clk PIN_B9) is the 50-MHz oscillator on the
board, which generates the input clock for the reference design
through a PLL
For more information on configuring the FPGA, refer to
Configuration" on page
Current sense resistors (0.010 Ohms +/- 1%) are installed at location JP6
(FPGA core power) and JP3 (FPGA I/O power + other device I/O power).
With a digital multimeter set to the mV measurement range, the resistor
at location JP6 can be used to measure the core power. The resistor at
location JP3 can be used to measure the I/O power.
Core Version a.b.c variable
State
00
01
10
11
2–3.
% of Design Used
25%
50%
75%
100%
Tables 4–2
"FPGA
Altera Corporation
April 2007