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Using the Watchdog Timer in XMC7000 family MCUs
Multi-counter WDT
3
Multi-counter WDT
The MCWDT includes three subcounters: Subcounters 0, 1, and 2.
Subcounter 0 and Subcounter 1 are 16-bit counters, which behave like the basic WDT. Window mode and pre-
warning interrupts are supported. If any window timing violation occurs, a FAULT or a reset after a FAULT can
be generated if not handled within a timeout timing.
Subcounter 2 is a 32-bit counter, which can be configured to generate an interrupt when one of the pre-defined
counter bits toggles. Both types of counters operate during Active, Sleep, and DeepSleep modes. They are not
available during Hibernate mode.
Figure 8
illustrates the block diagram of the MCWDT with all three subcounters.
LFCLK
MCWDTx_CNT0 (16-bit Counter)
Subcounter 0
Count
16
Figure 8
MCWDT block diagram
3.1
Source clock
The source clock that can be selected for MCWDT is LFCLK, which can be one of the following clock sources:
ILO0/1: Internal low-speed oscillator (32.768 kHz nom.) with relatively poor accuracy
•
WCO: Low-frequency watch crystal oscillator (32.768 kHz nom.)
•
ECO: High-frequency crystal oscillator (4–33.33 MHz nom.)
•
3.2
Register protection in MCWDT
Changing the registers related to MCWDT requires an UNLOCK sequence of the MCWDT_LOCK[1:0] bits located
in the LOCK register. The following access sequence must be performed for unlocking the following:
Subcounter 2: CTR2_CTL, CTR2_CONFIG, and CTR2_CNT registers
Application Note
MCWDTx_CNT1 (16-bit Counter)
Subcounter 1
Count <
MCWDTx_CTR0_LOWER_LIMIT
Count ==
MCWDTx_CTR0_WARN_LIMIT
Count >=
Count == 3
MCWDTx_CTR0_UPPER_LIMIT
Count
Count <
MCWDTx_CTR1_LOWER_LIMIT
Count ==
MCWDTx_CTR1_WARN_LIMIT
16
Count >=
Count == 3
MCWDTx_CTR1_UPPER_LIMIT
14 of 33
MCWDTx_CNT2 (32-bit Counter)
Subcounter 2
Count
32
MCWDTx_CTR2_CONFIG.
BITS
5
MCWDT
MCWDTx_CTR2_CONFIG.ACT
Mode
ION
Configuration
MCWDTx_INTR.CTR2_INT
Timeout
002-33887 Rev. *A
INTERRUPT
FAULT
RESET
2022-05-25
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