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ADSP-CM411F/412F/413F/416F/417F/418F/419F
4.
17000038 - M0 DMA Debug Halt Is Not Functional:
DESCRIPTION:
The M0 system's DMA debug logic that halts the DMA traffic does not function when a cross trigger unit halts. The DMA operations may
continue in real-time during debug halt.
WORKAROUND:
None.
APPLIES TO REVISION(S):
0.0
5.
17000040 - Internal LDO Increases VDD_INT:
DESCRIPTION:
The internal LDO increases VDD_INT by 250 mV (approximately).
WORKAROUND:
Run the flash info block initialization code each time the flash info block is erased. This modifies the internal LDO register to adjust the
voltage. It is available in the EVAL-CM41X-EZBRD/EVAL-CM41X-EZLITE evaluation platform Board Support Package (BSP). For more
information about how to program the flash info block, refer to the IAR projects located in the ProgramInfoSpace directory.
APPLIES TO REVISION(S):
0.0
6.
17000041 - Incorrect VMU Voltage Trip Values:
DESCRIPTION:
The most significant bit of the voltage trim values for the VDD_EXT and VDD_INT power supply trip levels are not programmed at power-
on-reset. As a result of this,
1. The VMU may detect a fault when the VDD_EXT and VDD_INT voltage levels are within specified range, and/or
2. The VMU may not detect the VDD_EXT and VDD_INT voltage levels operating outside the specified range.
WORKAROUND:
A software patch available in the startup.c file in the EVAL-CM41X-EZBRD/EVAL-CM41X-EZLITE evaluation platform Board Support
Package (BSP) trims the VMU.
APPLIES TO REVISION(S):
0.0
7.
17000042 - Oscillator Watch Dog Frequency Is Not Correct:
DESCRIPTION:
The trim values for the Oscillator Watch Dog (OSCWD) are not loaded properly at boot time, resulting in an incorrect OSCWD frequency.
WORKAROUND:
Manually load the correct trim values for OSCWD as shown in the following code:
#define BITM_TEPADS_PCFG0_AUXTRMEN 0x00010000
*pREG_PADS1_PCFG0 |= BITM_TEPADS_PCFG0_AUXTRMEN;
*pREG_PADS1_PCFG0 &= ~BITM_TEPADS_PCFG0_AUXTRMEN;
APPLIES TO REVISION(S):
0.0
NR004483C | Page 4 of 12 | July 2017
Silicon Anomaly List
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