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Analog Devices ADSP-CM411F Manual page 3

Mixed-signal control processor with arm cortex-m4/m0 and 16-bit adcs

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Silicon Anomaly List
DETAILED LIST OF SILICON ANOMALIES
The following list details all known silicon anomalies for the ADSP-CM411F/412F/413F/416F/417F/418F/419F including a description,
workaround, and identification of applicable product revisions.
1.
17000033 - SMC Byte Enable Signals Tri-State during Read Operations:
DESCRIPTION:
During SMC read operations, the byte enable signals (SMC0_ABE0 and SMC0_ABE1) are tri-stated instead of being driven low. Therefore,
when an 8-bit SMC write access is followed by a 16-bit or 32-bit read access, the read access may fail if the device requires active low byte
enable signals during read operations.
WORKAROUND:
While interfacing with the external SRAM, the SRAM byte enable signals can be driven low during read operations using external logic as
shown in the figure.
For SMC read operations, the SMC0_AOE signal is low. This drives the SRAM_BHE and SRAM_BLE signals low.
This external logic does not affect the SMC write operations, as the SMC0_AOE signal is high during write operations.
APPLIES TO REVISION(S):
0.0
2.
17000035 - Timer0 Status Interrupt Is Not Functional:
DESCRIPTION:
SYSBLK_SISTAT15.TIMER0_STAT bit is always read as 0. Therefore, Timer0 Status Interrupt is not functional.
WORKAROUND:
None.
APPLIES TO REVISION(S):
0.0
3.
17000036 - JTAG May Inadvertently Enter EXTEST Mode:
DESCRIPTION:
When performing a JTAG instruction register scan in multiple parts using the Pause-IR JTAG state, the JTAG controller erroneously enters
the EXTEST state while in the Pause-IR state. The I/O pins may incorrectly drive the rest of the system for multiple JTAG cycles.
WORKAROUND:
Using Pause-IR to break the instruction scan into parts must be avoided. If Pause-IR is used, ensure the ADI JTAG Instruction Register does
not have a value of b'00000 at the pause point. When in the Exit-IR state, if the ADI JTAG Instruction Register contains a value of b'00000,
the JTAG clock must not be stopped. This leaves the I/O pins in an undetermined state until the JTAG clocks resume.
APPLIES TO REVISION(S):
0.0
ADSP-CM411F/412F/413F/416F/417F/418F/419F
NR004483C | Page 3 of 12 | July 2017

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