Xilinx Alveo U200 Getting Started page 32

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Test 3 [0000:02:00.1]
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Test Status
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Test 4 [0000:02:00.1]
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Xclbin
test/verify.xclbin
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Test 5 [0000:02:00.1]
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Details
9160.052688 MB/s
12070.525345 MB/s
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Test 6 [0000:02:00.1]
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Xclbin
test/verify.xclbin
Testcase
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Test 7 [0000:02:00.1]
Description
Xclbin
test/bandwidth.xclbin
Testcase
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Test 8 [0000:02:00.1]
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Test 9 [0000:02:00.1]
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Test 10 [0000:02:00.1]
Description
UG1301 (v2.2) August 19, 2022
Getting Started with Alveo Accelerator Cards
: SC version
: Check if SC firmware is up-to-date
: [PASSED]
: Verify kernel
: Run 'Hello World' kernel test
: /opt/xilinx/firmware/u200/gen3x16-xdma/base/
: /opt/xilinx/xrt/test/validate.exe
: [PASSED]
: DMA
: Run dma test
: Host -> PCIe -> FPGA write bandwidth =
Host <- PCIe <- FPGA read bandwidth =
: [PASSED]
: iops
: Run scheduler performance measure test
: /opt/xilinx/firmware/u200/gen3x16-xdma/base/
: /opt/xilinx/xrt/test/xcl_iops_test.exe
: IOPS: 490653 (verify)
: [PASSED]
: Bandwidth kernel
: Run 'bandwidth kernel' and check the throughput
: /opt/xilinx/firmware/u200/gen3x16-xdma/base/
: /opt/xilinx/xrt/test/kernel_bw.exe
: Maximum throughput: 67188.9MB/s
: [PASSED]
: Peer to peer bar
: Run P2P test
: P2P bar is not enabled
: [SKIPPED]
: Memory to memory DMA
: Run M2M test
: bank0 -> bank1 M2M bandwidth: 11995.14 MB/s
bank0 -> bank2 M2M bandwidth: 12608.33 MB/s
bank0 -> bank3 M2M bandwidth: 12604.45 MB/s
bank1 -> bank2 M2M bandwidth: 12609.77 MB/s
bank1 -> bank3 M2M bandwidth: 12527.74 MB/s
bank2 -> bank3 M2M bandwidth: 12439.32 MB/s
: [PASSED]
: Host memory bandwidth test
: Run 'bandwidth kernel' when host memory is
Chapter 5: Card Bring-Up and Validation
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