Xilinx Alveo U200 User Manual
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Xilinx Alveo U200 User Manual

Accelerator cards
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Alveo U200 and U250
Accelerator Cards
User Guide
UG1289 (v1.1.1) November 20, 2019

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Summary of Contents for Xilinx Alveo U200

  • Page 1 Alveo U200 and U250 Accelerator Cards User Guide UG1289 (v1.1.1) November 20, 2019...

  • Page 2: Revision History

    Editorial updates only. No technical content updates. 10/31/2019 Version 1.1 All sections. Updated to the Vitis™ unified software platform throughout. 02/15/2019 Version 1.0 Initial Xilinx release. UG1289 (v1.1.1) November 20, 2019 www.xilinx.com Send Feedback Alveo U200 and U250 Accelerator Cards...

  • Page 3: Table Of Contents

    FT4232HQ USB-UART Interface....................17 PCI Express Endpoint........................17 QSFP28 Module Connectors....................18 I2C Bus............................18 Status LEDs..........................19 Card Power System........................19 Appendix A: Xilinx Design Constraints (XDC) File ........20 Appendix B: Regulatory and Compliance Information ......21 CE Directives..........................21 CE Standards..........................21 Compliance Markings.......................
  • Page 4 Xilinx Resources.........................23 Documentation Navigator and Design Hubs.................23 References..........................23 Please Read: Important Legal Notices................... 25 UG1289 (v1.1.1) November 20, 2019 www.xilinx.com Send Feedback Alveo U200 and U250 Accelerator Cards...

  • Page 5: Chapter 1: Introduction

    UltraScale+™ technology. These cards accelerate compute-intensive applications such as machine learning, data analytics, video processing, and more. The Alveo U200/U250 Data Center accelerator cards are available in passive and active cooling configurations. The following figure shows a passively cooled Alveo U200 accelerator card.
  • Page 6 Figure 1: Alveo U200 Data Center Accelerator Card (Passive Cooling) X23434-102419 CAUTION! The Alveo U200/U250 accelerator card with passive cooling is designed to be installed into a data center server, where controlled air flow provides direct cooling. Due to the card enclosure, switches are not accessible and LEDs are not visible (except for the triple-LED module DS3 that protrudes through the left front end PCIe bracket).

  • Page 7: Block Diagram

    Chapter 1: Introduction Block Diagram The block diagram of the Alveo U200/U250 accelerator card is shown in the following figure. Figure 2: Card Block Diagram 288-pin DIMM interface 64-bit + ECC dual rank support x4/x8 UDIMM support PC4-2400 compatible Clocks...
  • Page 8 • Onboard reprogrammable flash configuration memory • Front panel JTAG and universal asynchronous receiver-transmitter (UART) access through the USB port • FPGA configurable over USB/JTAG and Quad SPI configuration flash memory UG1289 (v1.1.1) November 20, 2019 www.xilinx.com Send Feedback Alveo U200 and U250 Accelerator Cards...

  • Page 9: Card Specifications

    Vitis™ unified software platform. However, traditional design flows, such as RTL or HLx are also supported using the Vivado ® Design Suite tools. The following figure shows a summary of the design flows. UG1289 (v1.1.1) November 20, 2019 www.xilinx.com Send Feedback Alveo U200 and U250 Accelerator Cards...
  • Page 10 In the Vivado Design Suite, select Create New Project →  RTL Project, and then select the Alveo Data Center accelerator U200 card as shown in the following figure. UG1289 (v1.1.1) November 20, 2019 www.xilinx.com Send Feedback Alveo U200 and U250 Accelerator Cards...
  • Page 11 Boards tab, the following figures appear. The RTL-based project can now be created. Figure 5: Alveo Data Center Accelerator U200 Card New Project Summary X22261-012519 UG1289 (v1.1.1) November 20, 2019 www.xilinx.com Send Feedback Alveo U200 and U250 Accelerator Cards...
  • Page 12 0x01002000 and the interface set to spix4 when creating the MCS file. Details on adding this to the MCS file can be found in the UltraScale Architecture Configuration User Guide (UG570). UG1289 (v1.1.1) November 20, 2019 www.xilinx.com Send Feedback Alveo U200 and U250 Accelerator Cards...
  • Page 13 3. After programming has completed, disconnect the card in the hardware manager, and disconnect the USB cable from the Alveo accelerator card. 4. Perform a cold reboot on the host machine to complete the card update. UG1289 (v1.1.1) November 20, 2019 www.xilinx.com Send Feedback Alveo U200 and U250 Accelerator Cards...

  • Page 14: Chapter 2: Card Installation And Configuration

    • Put the adapter down only on an antistatic surface such as the bag supplied in your kit. • If you are returning the adapter to Xilinx Product Support, place it back in its antistatic bag immediately. Installing Alveo Data Center Accelerator...

  • Page 15: Fpga Configuration

    Chapter 2: Card Installation and Configuration FPGA Configuration The Alveo U200/U250 accelerator card supports two UltraScale+™ FPGA configuration modes: • Quad SPI flash memory • JTAG using USB JTAG configuration port (USB J13/FT4232H U27) The FPGA bank 0 mode pins are hardwired to M[2:0] = 001 master SPI mode with pull-up/down resistors.

  • Page 16: Chapter 3: Card Component Description

    Card Component Description This chapter provides a functional description of the components of the Alveo™ U200/U250 Data Center accelerator card. UltraScale+ FPGA The Alveo U200 accelerator card is populated with the Virtex ® UltraScale+™ XCU200- L2FSGD2104E FPGA. The Alveo U250 accelerator card is populated with the Virtex UltraScale+ XCU250- L2FIGD2104E FPGA.

  • Page 17: Usb Jtag Interface

    The Alveo accelerator card provides access to the FPGA device via the JTAG interface. FPGA configuration is available through the Vivado ® hardware manager, which accesses the on- board USB-to-JTAG FT4232HQ bridge device. The micro-AB USB connector on the Alveo U200/ ® U250 accelerator card PCIe panel/bracket provides external device programming access.

  • Page 18: Qsfp28 Module Connectors

    Each connector is housed within a single QSFP cage assembly. The QSFP+ connectors are accessible via the I2C interface on the Alveo U200/U250 accelerator cards. The QSFP connector’s sideband signals are accessible directly from the FPGA. The MODSELL, RESETL, MODPRSL, INTL, and LPMODE sideband signals are defined in the small form factor (SFF) specifications listed below.

  • Page 19: Status Leds

    FPGA design process which begins after the Alveo Data Center accelerator card is selected from the Vivado Design Suite Boards tab. Refer to Design Flows for more information. UG1289 (v1.1.1) November 20, 2019 www.xilinx.com Send Feedback Alveo U200 and U250 Accelerator Cards...

  • Page 20: Appendix A: Xilinx Design Constraints (Xdc) File

    Appendix A: Xilinx Design Constraints (XDC) File Appendix A Xilinx Design Constraints (XDC) File RTL users can reference the Vivado Design Suite User Guide: Using Constraints (UG903) for more information. The Alveo accelerator card XDC files are available for download from their respective websites along with this user guide.

  • Page 21: Appendix B: Regulatory And Compliance Information

    Safety IEC 60950-1, 2nd Edition, 2014, Information technology equipment – Safety, Part 1: General requirements UG1289 (v1.1.1) November 20, 2019 www.xilinx.com Send Feedback Alveo U200 and U250 Accelerator Cards...

  • Page 22: Compliance Markings

    Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end-of-life.

  • Page 23: Appendix C: Additional Resources And Legal Notices

    • On Windows, select Start → All Programs → Xilinx Design Tools → DocNav. • At the Linux command prompt, enter docnav. Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs: •...
  • Page 24 3. Alveo Data Center Accelerator Card - Known Issues and General Information 71752) Supplemental Documents The following Xilinx document provide supplemental material useful with this guide. • UltraFast Design Methodology Guide for the Vivado Design Suite (UG949) • Vivado Design Suite User Guide: System-Level Design Entry (UG895) •...
  • Page 25 IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for...
  • Page 26 Appendix C: Additional Resources and Legal Notices Copyright © Copyright 2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

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Alveo u250

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