Advantech iDAQ-934 User Manual page 41

The start and stop of the generation are controlled by the start trigger and stop trig-
ger, respectively. When configuration is completed, the acquisition engine of the
iDAQ chassis is at standby state. After receiving a start trigger, generation becomes
active and each rising edge of the sample clock converts one analog output sample.
The generation active period lasts until a stop trigger is received, which ends the gen-
eration. This is shown in Figure 3.32.
Figure 3.32 Start and stop of the digital output waveform generation
The start and stop of generation can also be delayed in number of samples after
receiving the corresponding trigger signal. As shown in Figure 3.33, the start of gen-
eration is delayed by 3 samples after receiving a start trigger, and the stop of genera-
tion is delayed by 2 samples after receiving a stop trigger.
Figure 3.33 Start and stop of the digital output waveform generation with delay
Refer to 3.1.1 Signal Routing for possible signal routings and configurations for these
timing signals (start trigger, stop trigger, and sample clock).
Buffered digital output waveform generation has several advantages over static digi-
tal output update:
The start and stop time of generation (or duration of the generation) can be pre-

cisely controlled by hardware trigger signals.
Update rate can be much higher by using hardware sample clock signal.

Time between samples is deterministic.

31 iDAQ-934_964 User Manual