Tektronix PM 101 Instruction Manual page 30

Theory of Operation-PM 101
LOOK
/S E L P
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A
D D
From S.U.T.
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D A _ T _ A __ _
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From S.U.T.
/STOPS. U. T. is a buffered (A 1 U5031) output version of
the input / HALT S.U.T. from the Logic Analyzer. It is
protected by a spark-gap, a 100
(A1R6050), and clamping
A 1 CR6050). (This signal is labeled "HALT" on the Per­
sonality Module cover.)
Sel f T est Stimul u s Circuitry
The Self Test Stimulus Circuitry is located on board A2
and appears on schematic 2.
The Self Test Stimulus Circuitry consists of a free
running 16-bit counter (A2U5020, A2U4020, A2U2020,
and A2U1020) whose input, T1 (A2U3020-4) is oscillating
at a frequency of approximately 10 MHz.
4-4
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R E ss-- D--7(
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From Logic Analyzer
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1
1
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Rg. 4-2. How the Logic Analyzer reads the ROM.
n
series resistor
diodes (A1CR6052 and
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C>-k ____ _ _
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V U
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D _ A _ TA _
____,1 >-t( ____ _ _
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1
From PM ROM
1
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READ TIME
T1 through T17 are the free-running counter outputs.
T1' is the approximately 10 MHz clock rate generated by
the A2O3015 circuitry and buffered by A2U3020, while T17
is the slowest bit, running at about 76 Hz. T2 through T17
and T21 are buffered by A2U4030 and A2U1030.
T18, T19 and T20 are ripple carry outputs from
A2U5020, A2U4020, and A2U2020, the first three I Cs in the
four-IC counter. These outputs are buffered by A2U3020.
See Sections 5 and 6 for information on how to use the
Self Test Stirpulus outputs.
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From S.U. T.
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REV JUN 1981
2917-06A