Instruction Fetch And Demultiplexing; User Clock Synthesis - Tektronix PM 101 Instruction Manual

Operating Instructions-PM 101
the CONTROL column. Control lines C4 and C5 may also
be used in word recognizer event definition, though they
are not stored. C4 through C9 can be used for clock
qualification, which makes them useful for state clock
generation, where the logical ANDing of the selected
qualifiers and the input clock edge selects acquisition
strobes (the State Clock) from the input clock signals and
thereby limits the data collected. C6-C9 also have a role
in USER CLOCK SYNTHESIS; see that subsection below.
All clock qualifiers must meet set-up and hold time
specifications relative to the PM 101 clock input.
Refer to Sections 3 and 5.
When using USER CLOCK QUALification and USER
CLOCK SYNTHESIS, the clock qualifier must be true
when the clock synthesizer enables an Acquisition Strobe.
It is possible to enter contradictory program instructions.
If all clocks are disqualified, a NO CLOCK message will be
displayed. If all data is disqualified, a NO DATA AC­
QUI RED message appears when the program is stopped.
Instruction Fetch and Demultiplexing. The PM 101
does not have circuitry for decoding Instruction Fetch
cycles or demultiplexing busses because it is not specific
to any particular protocol. Nonetheless, appropriately
connected control lines can provide qualification i nforma­
tion which allows the Logic Analyzer to derive Instruction
Fetch cycles or demultiplexing timing. Knowledge of the
workings of the system under test and appropriate
qualification can be used to identify almost any state of the
system and to collect data only while the system is in that
state. The data collected may be limited by either clock
qualification in the trigger command or word recognizer
event definition.
Clock. The Clock input Ii ne to the PM 101 is used to
detect the basic timebase of the system under test. This
clock is transmitted by the PM 101 for use as the data
acquisition timebase after any desired polarity selection
and qualification have been applied. The 7D02 Logic
Analyzer has the ability to divide the clock or delay the
clock from the system-under-test by two, three, or four, to
select the rising or falling edge, and to AND the selected
clock edge with a control word selected from C4-C9.
Without user intervention, the default values imbedded in
the PM 101 's ROM are: no division, positive edge, and all
"Don't Cares" (Xs) for C4-C9. These default values may
be varied by entries in the User Clock Qualification field in
the Program mode.
User Clock Synthesis. ESYNC (C6 or CB) allows
synchronization of the 7D02 Clock Synthesizer to the
timebase of the system-under test. The ESYNC signal is
the reference for both the DIVIDE BY N mode and the
DELAY BY N mode.
NOTE
If USER CLOCK SYNTHESIS is selected in the 7D02,
the user then has a choice between DELAY CLOCK BY N,
where N may be 0, 1, 2, 3, or 4, and DIVIDE CLOCK BY N,
where N may equal 1, 2, 3, or 4. A del ay ofO or a divide by 1
correspond to the inactivated states of these modes.
Do not use the ESYNC or WAIT lines when dividin g
by 1 or delayin g by 0.
If the user selects DELAY CLOCK BY N, one acquisi­
tion strobe (State Clock) will occur for every ESYNC,
delayed by N input clock pulses. Refer to Fig. 2-1 and 2-3.
If the user selects DIVIDE CLOCK BY N, however, the
Acquisition Strobe will occur on the N-1th input clock
pulse after the end of the ESYNC signal, and at one Nth of
the frequency of the input clock. The clock will continue at
that frequency without further ESYNC signals. Refer to
Fig. 2-2 and 2-3. In this mode it is assumed that ESYNC is
asserted on the first phase of a multi-phase clock system
and that it is desired to generate the 7D02 acquisition
strobe (State Clock) on the last phase.
If ESYNC is repetitive, it should be regular and asserted
at the same place in the input clock cycle of a system with a
multi phase clock. If these conditions are not met, the
clock phase may become un-synchronized or extra
acquisition strobes (State Clocks) may be generated.
Normally, when a repetitive ESYNC signal is available, the
delay-by mode is most useful. Where no repetitive ESYNC
is available, the divide-by mode is most useful, with
ESYNC connected to some signal such as "Power-up
Reset".
WAIT (C7 or C9) signals in both modes simply delay the
next acquisition strobe (State Clock) by one input clock
pulse for every input clock pulse that occurs while WAIT is
asserted. See Fig. 2-1 and 2-2.
WAIT also qualifies acquisition strobes (the State
Clock), inhibiting them even when all H1e ANDed Clock
Qualifiers are true. Refer to Fig. 2-3.
NOTE
If both WAIT and ESYNC are asserted at the same
time, only the WAIT si g nal will be effective. See
Fi g . 2-3.
NOTE