User Clock Synthesis-Delay By; User Clock Synthesis-Divide By - Tektronix PM 101 Instruction Manual

INPUT CLOCK
ESYNC
WAIT
AQUISITION
STROBE
(STATE CLOCK)
� -
.----
INPUT CLOCK
ESYNC
WAIT
ACQUISITION
STROBE
(STATE CLOCK)
@
__ _ r, _______
Fig. 2-1. User Clock Synthesis-Delay by 2.
r, _____ r7 _____ _
_____J"7 __
Fig. 2-2. User Clock Synthesis-Divide by 2.
r-, __________
Operating Instructions-PM 101
r, ____ _
2917-02
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2917-03
2-3