Table of Contents
Advertisement
General Theory of Operation
The primary function of a Personality Module is to
collect data from the System-Under-Test and transfer it to
the Logic Analyzer along with appropriate format and
display information.
In the PM 101 General Purpose Personality Module this
result is achieved by circuitry in one of five functional
areas:
- Data Transfer Circuitry, including data, address, and
control Ii nes,
- Clock Transmission Circuitry, which converts the
TTL "CLK IN" to ECL for rapid and buffered
differential transmission to the Logic Analyzer,
- ROM Circuitry, which consists of 2k of Personality
ROM with provision for a 2k, 4k, or 8k Custom ROM
developed for custom disassembly,
Control Circuitry, which interprets the status of the
LOOK and /SEL P lines and buffers /HALT S.U.T.
into /STOP S.U.T.,
- Self Test Stimulus Circuitry, which generates
signals for t he module-analyzer system diagnostics.
A
in front of a signal name or part of a signal name
"/"
indicates that the signal is active when low. E.g., R/W
implies
0
Write
-
1
Read
-
Figure 4-1 is a Circuit Block Diagram which organizes
the circuitry and shows the signal flow. It should be useful
in
gaining an overview of circuit
troubleshooting certain problems, and understanding the
Detailed Circuit Descriptions which follow.
@
THEORY OF OPERATION
NOTE
operation,
DETAILED CIRCUIT DESCRIPTION
Data Transfer Circuitry
The data transfer circuitry is on board A 1 and appears
on schematic 1 A.
All Data (Dl0-DI 15), Address (Al0-Al23), and Control
(Cl0-Cl9) lines are protected against static discharge,
which could damage the Personality Module or Logic
Analyzer circuitry, by hybrid !Cs containing spark-gaps,
series resistors, and clamp diodes. Each hybrid protects
four input Ii nes. The Control Ii nes pass through A 1 U5045,
A 1 U4050, and A 1 U4043. The Data Ii nes pass through
A 1 U2033, A 1 U1052, A 1 U2043, and A 1U1041. The Address
Ii nes are protected by A 1 U4036, A 1 U4032, A 1 U3034,
A 1 U3042, A 1 U3044 and A 1 U3040.
After passing through the protection hybrids, the Data,
Address, and Control inputs are buffered by 7 4LS244
Octal Buffer ICs, so that the System-Under-Test is only
subjected to a small amount of loading. The Control lines
are buffered by A 1 U5041 and A 1 U4041. The Data Ii nes are
buffered by A 1 U2031 and A 1 U2041. The Address Ii nes are
buffered by A 1 U5031, A 1 U3031, A 1 U3041, and A 1 U4041.
When these buffers are in a "O" state and the voltage is
increasing, they require approximately 1.6 V of input to
switch them to a "1" state. However, when they are in a "1"
state and the input voltage is decreasing, it must go as low
as approximately 1.2 V before being interpreted as a "O".
This hysteresis effect provides enhanced protection
against noise and glitches on the Ii ne.
The buffers are matched to the impedance of the lines
they drive by 68 O series terminating resistors.
Clock Transmission Circuitry
in
The clock transmission circuitry is on board A 1 and
appears on schematic 1 B.
Section 4-PM 101
4-1
Advertisement
Table of Contents
Troubleshooting
