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2.3. Power Supply
This board operates from single DC 3.3 V (V33A) power supply from CNA.
Internally required 1.2 [V] is generated by on-board voltage regulators.
The external power supply should be sufficient and stabilized. Please do not apply
over 3.3 V voltage.
VIO(B), Vccio of CNB I/Os is not connected to V33A. Please apply voltage suit your
design from CNB.
For more details, please refer to circuit schematics and FPGA data sheet.
2.4. Clock
50 MHz (U1) oscillator is equipped as on-board clock. External clock can be input
from user I/O connectors.
2.5. JTAG Connector
This connector is used to configure the FPGA and program the configuration device
in-system. Pin assignment is as follows. You can use Xilinx download cable.
CN1
Notice
XCM-306 Series v1.0
Pin No.
Signal Name
1
GND
2
TCK
3
TDO
4
TMS
5
VREF
6
TDI
7
GND
Please pay attention not to attach cables in reverse.
Direction
I/O
IN
OUT
IN
OUT
IN
I/O
4
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