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3.3. Power Supply
This board operates from single DC 3.3 V power supply from CNA and CNB.
Internally required 2.5[V], 1.8[V], 1.2[V] and 0.9[V] are generated by on-board
voltage regulators.
The vcco of BANK B is not connected to 3.3V. Please input given voltage from CNB.
By shorting JP1, 3.3V is available. Or by switching PJ3, 2.5V is available.
The external power supply should be sufficient and stabilized. Please do not apply
over 3.3V voltage.
For more details, please refer to circuit schematics and FPGA data sheet.
3.4. Clock
50 MHz (U8) and 30 MHz (U9) oscillators are equipped as on-board clock. External
clock can be input from user I/O connectors (CNA, CNB).
For more details, please refer to circuit schematic.
3.5. JTAG Connector
This connector is used to configure the FPGA and program the configuration device
in-system. Pin assignment is as follows. You can use Xilinx download cable.
CN2
Notice
XCM-020 Series v1.0
Pin No.
Signal Name
1
GND
2
TCK
3
TDO
4
TMS
5
VCC (3.3V)
6
TDI
7
GND
Please pay attention not to attach cables in reverse.
Direction
I/O
IN
OUT
IN
OUT (POW)
IN
I/O
6
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