Control Output Period Setting (Buffer Memory Address: 2F H , 4F H , 6F H , 8F H ); Primary Delay Digital Filter Setting (Buffer Memory Address: 30 H , 50 H , 70 H , 90 H ) - Mitsubishi Electric MELSEC Q Series User Manual

3 SPECIFICATIONS
3.5.21 Control output period setting (buffer memory address: 2F
3.5.22 Primary delay digital filter setting (buffer memory address: 30
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(1) Sets the pulse cycle (ON/OFF cycle) of the transistor output.
Transistor output
(2) The setting range is 1 to 100 (1 to 100s).
(3) The ON time of the control output period is found by multiplying the control output
period by the manipulated value (%) calculated by PID operation. (Refer to
Section 3.5.6.)
(1) The primary delay digital filter is designed to absorb sudden changes when the
process value (PV) is input in a pulse format.
Process value
Process value
(2) As the primary delay digital filter setting (filter setting time), specify the time for the
PV value to change 63.3%.
Process value
Control PV value
63.3%
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Manipulated value (%)
ON
OFF
Control output period
Primary delay digital filter setting
MELSEC-Q
, 4F , 6F , 8F )
H H H H
, 50 , 70 , 90 )
H H H H
t
t
t
t
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