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(2) Separate Bus, With Wait, Accessing External Memory Area
Table 5.3 and Figure 5.2 show the bus timing in the memory expansion mode and the microprocessor
mode (with wait, accessing external memory area).
Table 5.3 Memory expansion mode and microprocessor mode (with wait, external memory area)
Symbol
Td (BCLK-AD)
Address output delay time
Th (BCLK-AD)
Address output hold time (BCLK standard)
Th (RD-AD)
Address output hold time (RD standard)
Th (WR-AD)
Address output hold time (WR standard)
Td (BCLK-CS)
Chip-select output delay time
Th (BCLK-CS)
Chip-select output hold time (BCLK standard)
Td (BCLK-ALE)
ALE signal output delay time
Th (BCLK-ALE)
ALE signal output hold time
Td (BCLK-RD)
RD signal output delay time
Th (BCLK-RD)
RD signal output hold time
Td (BCLK-WR)
WR signal output delay time
Th (BCLK-WR)
WR signal output hold time
Td (BCLK-DB)
Data output delay time (BCLK standard)
Th (BCLK-DB)
Data output hold time (BCLK standard)
Td (DB-WR)
Data output delay time (WR standard)
Th (WR-DB)
Data output hold time (WR standard)
*1 Calculated by the following formula according to the frequency of BCLK.
9
10
Td (DB-WR)=
f(BCLK)
*2 Calculated by the following formula according to the frequency of BCLK.
9
10
Td (DB-WR)=
f(BCLK)
Item
-40 [ns]
-42 [ns]
( 49 / 72 )
Actual MCU
This product
[ns]
[ns]
Min.
Max.
Min.
Max.
25
52
4
See left
0
See left
0
See left
25
34
4
See left
25
See left
-4
See left
25
32
0
See left
25
32
0
See left
40
57
4
See left
(*1)
(*2)
0
See left
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