Renesas Emulation Pod M306V2T-RPD-E User Manual page 56

Common to "with wait" and "no-wait" (actual MCU)
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5 to P5
0 2
Common to "with wait" and "no-wait" (this product)
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5 to P5
0 2
Note 1. P0 to P5 will be high-impedance regardless of the input level of BYTE pin and ports P4
0 2
selection bit (PM06) of the processor mode register 0.
Note 2. This product will be high-impedance delaying by 2.5 cycles than the actual MCU.
Note 3. The setup time of HOLD is defined by the startup of BCLK, differently from that of actual MCUs.
Figure 5.5 Timing requirements
Conditions:
• V =5V
CC
• Input timing voltage: V
IL
• Output timing voltage: V
( 54 / 72 )
to P4
0
=1.0V, V =4.0V
IH
=2.5V, V =2.5V
OL OH
function
3