Sdram - Renesas M3A-HS85 User Manual

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2.3.3 SDRAM

The M3A-HS85 can mount 16Mbytes of SDRAM (Not mounted). In the M3A-HS85 specification, 3.3V power is
supplied to SDRAM so that SH7285 should be used in 3.3V when SDRAM is mounted (CPU power supply switch
jumper (JP1) should be set to " 2-3 " ). The SDRAM is controlled by the bus state controller built into SH7285.
Table 2.3.2 lists the SDRAM specifications. Figure 2.3.2 shows the block diagram for the connection between
SH7285 and SDRAM.
Specification
Configuration
Capacity
Access Time
CAS Latency
Refresh Interval
Low Address
Column Address
Number of Banks
SH7285
PC12/A12-PC1/A1
PD15/D15-PD0/D0
Figure 2.3.2 Block Diagram for the Connection Between SH7285 and SDRAM
Rev.1.04 2008.7.10
REJ10J1564-0104
Table 2.3.2 SDRAM Specifications
2M words x 16 bits x 4 banks (1pc.)
16 Mbytes
5.4ns
2 (at 40MHz bus clock)
4096 refresh cycle every 64ms
A11- A0
A8 - A0
4-bank operation controlled by BA0 and BA1
PC14/A14
PC13/A13
PA15/CK
PA9/CKE
PB12/CS3
PA6/RASL
PA7/CASL
PA8/RDWR
PA12/DQMLU
PA13/DQMLL
Content
SDRAM
(8M Word x 16bit)
BA1
BA1
BA0
BA0
11
A11-A0
- A 0 A11
CLK CLK
CKE CKE
CS# CS
R A S #
RAS
CAS
CAS
WE WE#
DQMU DQMU
DQML DQML
16
DQ15-DQ0
Functional Overview
2.3.3 SDRAM
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