Renesas M3A-HS85 User Manual page 14

32-bit risc microcomputers superh riscengine family / sh7285 group cpu board

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Logical space of the SH7285

(On-chip ROM enabled mode)

H'0000 0000

H'000B FFFF

H'000C 0000

H'01FF FFFF

H'0200 0000

H'03FF FFFF

H'0400 0000

H'07FF FFFF

H'0800 0000

H'0BFF FFFF

H'0C00 0000

H'0FFF FFFF

H'1000 0000

H'13FF FFFF

H'1400 0000

H'17FF FFFF

H'1800 0000

H'1BFF FFFF

H'1C00 0000

H'1FFF FFFF

H'2000 0000

H'801F FFFF

H'8020 F000

H'802F FFFF

H'8030 0000

H'FFF7 FFFF

H'FFF8 0000

H'FFF8 7FFF

H'FFF8 8000

H'FFFB FFFF

H'FFFC 0000

H'FFFC FFFF

H'FFFD 0000

H'FFFD FFFF

H'FFFE 0000

H'FFFF FFFF

[Notes]

*1：CS space to assign is selected according to software. CS space which can be selected at a

time is only one.

*2：It is initially not mounted.

Rev.1.04 2008.07.10

REJ10J1564-0104

MCU mode 2

On-chip ROM(768KB)

Reserved

CS0 space

CS1 space

CS2 space

CS3 space

CS4 space

CS5 space

CS6 space

CS7 space

Reserved

On-chip flash memory

writing/verify space

Reserved

On-chip RAM(32KB)

Reserved

SDRAM mode setting

Reserved

Peripheral I/O

Figure 1.7.3 Example Memory Mapping of SH7285 (MCU mode 2)

1.7 M3A-HS85 Memory Mapping

M3A-HS85 Memory Mapping

H'0000 0000

On-chip ROM(768KB)

H'000B FFFF

H'000C 0000

H'01FF FFFF

SRAM(2MB) *1 *2

H'0200 0000

H'03FF FFFF

H'0400 0000

H'07FF FFFF

SRAM(2MB) *1 *2

H'0800 0000

H'0BFF FFFF

H'0C00 0000

SDRAM(16MB) *2

H'0FFF FFFF

H'1000 0000

H'13FF FFFF

H'1400 0000

H'17FF FFFF

SRAM(2MB) *1 *2

H'1800 0000

H'1BFF FFFF

H'1C00 0000

H'1FFF FFFF

H'2000 0000

H'801F FFFF

H'8020 F000

On-chip flash memory

writing/verify space

H'802F FFFF

H'8030 0000

H'FFF7 FFFF

H'FFF8 0000

On-chip RAM(32KB)

H'FFF8 7FFF

H'FFF8 8000

H'FFFB FFFF

H'FFFC 0000

SDRAM mode setting

H'FFFC FFFF

H'FFFD 0000

H'FFFD FFFF

H'FFFE 0000

H'FFFF FFFF

Overview

Reserved

User area

Reserved

Peripheral I/O

1-10

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Renesas M3A-HS85 User Manual page 14

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