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1881M
Theory of Operation
5.3.2 Secondary Addressing in Data Space
Data is readout of the module via FASTBUS by first accessing the module through a primary address cycle
to Data Space and then performing subsequent read data cycles. In the default operational mode, secondary
addressing in Data Space is not relevant. A second operational mode, Memory Test Mode, is provided
which supports secondary addresses in Data Space and allows access to any buffer memory location within
the 8K Data Space.
5.3.2.1 Default Addressing Mode
The default addressing mode, which does not support secondary addressing in Data Space, is primarily
useful only if the FASTBUS readout method is a block transfer. In this mode, reads and writes to the Data
Space NTA are acknowledged but ignored.
For block transfers in this mode, each individual buffer appears similar to a FIFO. For example, assume
that the module has been prepared for readout (i.e. the FASTBUS Read Pointer is pointing to a the first
word in a valid event within the circular buffer and CSR5 has been loaded with the word count for that
event). The first data word transferred during a block read is the event header word. This header contains
the geographic (or logical) address, parity, and the absolute address (in the 16K word circular buffer
memory) of the last valid data word of the event being readout. The absolute address contains the buffer
number, RP, also available in CSR16, and the word count including the header word, RPA for the last
data word written to memory. Subsequent transfers produce the event data words in a similar manner to a
FIFO until CSR5 has decremented to zero and the module generates SS = 2.
RPA is incremented after each read to point the next word in the buffer during the block transfer. Random
reads from Data Space must be used with care since the location of RPA (not visible to FASTBUS) is not
known except under very specific circumstances. Random reads will increment the RPA and thus can be
used to readout the module in a way similar to a FIFO however no indication will be given when the end
last valid data word has been readout. The number of words to readout by this method must be
ascertained from the header word.
In the default readout mode, re-reads of a particular buffer are not directly supported since it is difficult to be
certain, after the event has initially readout via block transfer, what the value of RPA is. Re-read of a buffer
may be accomplished indirectly by manipulating RP via CSR16 and issuing a Load Next Event command.
5.3.2.2 Memory Test Mode (MTM)
Memory Test Mode is an operational mode selectable via CSR0 which supports secondary addressing in
Data Space. In this mode, the RPA portion of the FASTBUS Read Pointer is accessible as the Data Space
Next Transfer Address (NTA).
In MTM, the 1881M buffers must be thought of as a paged memory, circular buffer scheme, not a FIFO.
Random read or write data cycles may operate on any location addressable by the current RPA. By
manipulating RP (via CSR16) and NTA, any location in the 8K Data Space can be addressed for reads or
writes. This mode facilitates memory testing but may also serve as a very useful operating mode,
depending on the specific user application. As per the FASTBUS specification, RPA and therefore NTA
is only incremented during block reads. Block writes are not supported in the 1881M.
Block transfers are controlled in exactly the same way as with the default mode except that RPA is now
accessible as the Data Space NTA and may be set by the user. In all cases, CSR5 controls the number of
words transferred during a block transfer and RPA controls the address within the buffer where the transfer
will begin. RPA (and therefore NTA) is incremented with each word transferred during a block transfer. If
CSR5 > (2048 - RPA), then RPA will wrap around back to the beginning of the page.
Note: In contrast to MTM in the 1881, since the 1881M NTA appears as only 11 bits, there is no need for
the user to keep track of the Read Page to avoid accidentally changing the page to which the FASTBUS
Read Pointer is pointing. This allows existing software library routines that always write the secondary
address before beginning a transfer to operate without modification.
5-5
July 23, 1998
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