Data Space - LeCroy 1881M Manual

1881M
Product Description

2.7 Data Space

Data memory in the 1881M ADC is a 8K word circular buffer, organized in sixty four pages of 128 words
each. Data resulting from an event is stored in one of the sixty four buffers. Each event buffer contains
enough locations to hold the maximum data resulting from a single event (65 words). An event is defined
as the occurrence of a Gate without a clear within the fast clear window.
In the power-up or reset state, Memory Test Mode is disabled, and the 1881M data space consists of only
DSR0 from the FASTBUS point of view. Writes to the Data Space NTA have no effect. CSR16 controls
the read buffer, as well as the write buffer which will be used to store the next event readout of the
MTD133s. Only the data page portion of the buffers can be accessed. At power-up, or when a master
reset is issued, the read buffer will be 63, and the write buffer will be 0. Once an event occurs and is
buffered, the write buffer number is automatically incremented. CSR16 is a read-write register which can be
used to control the position of the read and write buffers. Under normal operating circumstances, it is not
necessary to change these buffers because it is done automatically. CSR16<10:8>, the read buffer, is
modified by the Load Next Event command and CSR16<2:0>, the write buffer, is modified by the
MTD133 readout circuitry (see figure 2-4).
When Memory Test Mode is enabled, any location within the 8K data space is directly accessible via
FASTBUS. At any particular time, there are 128 (one complete buffer) secondary addresses (DSRs)
available in data space. The buffer currently pointed to by CSR16 can be modified by the Load Next Event
command or by writing CSR16 directly. This mode can be very useful to determine exactly what is going
on within the unit when debugging the system and it may be used for normal operation. It should be
noted, however, that the unit will not be FASTBUS compliant, as the module's data space NTA will
move during priming operations (assuming Priming on LNE has been enabled).
CSR5<6:0> controls the number of words transferred in a block read. During normal data acquisition, a
Load Next Event both advances the read buffer to the next event, and loads CSR5<6:0> with the correct
word count for the event contained in the next buffer. This can be done for an entire crate of 1881Ms (and
1877s) by using a broadcast command. The maximum number of words transferred is limited to one full
buffer (128 words).
When the read pointer is one less than the write pointer (modulo 64) the buffers are considered empty.
When the read pointer and the write pointer are equal, the buffers are considered full. The condition "not
empty" is used for the Sparse Data Scan. The condition "full" is used to extend Conversion in Progress
(CIP) until the buffers are not full.
2-9 July 23, 1998