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Theory of Operation
5.2.1 Readout of MTDs
Readout of event time data from the MTDs begins after the end of run down. Data words that exceed their
respective sparsification threshold are written into the buffer currently pointed to by WP starting at the
location pointed to by WPA. If the module receives a Fast Clear during its programmed Fast Clear
Window, the event just buffered (or being buffered) is discarded - WP is not incremented and WPA is
cleared.
5.2.2 Organization of Data in Events
As data words are written to memory, the WPA is incremented until all data words have been readout of
the MTDs. CIP is then deasserted and a header word (which is the complete buffer address of the last data
word) is written into Write Page Address zero, the first memory location of the page. In this manner, all
events, once completely buffered, consist of a header word in the first memory location of a given buffer
(page) followed by the data words for that event. Further, since the header word contains the absolute
memory location one beyond the last data word for that event, it contains both the buffer number (within
the circular buffer structure) and the complete word count for that event including the header word itself. If
an event occurs which has no data words - a null event - a header word with a word count of one is still
written and the MTD Write Pointer is advanced to the beginning of the next buffer.
5.3 FASTBUS Access to Module
5.3.1 Control and Status Registers
Several Control and Status Registers (CSR's) control the configuration and operation of the 1881M. The
following is a list of the CSR's contained in the 1881M and a brief description of their function(s):
CSR0, CSR1 - primary control and configuration registers. These registers contain the
configuration bits for all operational modes of the 1881M. Additionally, CSR0 contains pulsed
bits which initiate operations specific to the module such as Master Reset, Load Next Event,
internal test cycles, etc.
CSR3 - Logical Address
CSR5 - Block transfer word count register. CSR5 controls the number of words which will be
transferred during a block transfer. A SS = 2 response is generated by the module when CSR5 has
decremented to zero during a block transfer. This register is read/write and may be loaded with an
arbitrary value up to 7Fh (one full buffer). CSR5 is loaded automatically with the word count for
the next event when the module is prepared for readout of an event using a LNE command.
CSR7 - Controls Class-N broadcast response
CSR16 - Buffer Status register. CSR16 contains the Read Page (RP) and Write Page (WP) of the
FASTBUS Read Pointer and the MTD Write Pointer, respectively. This register, therefore,
indicates to which buffer, in the circular buffer structure, each of the pointers is pointing. CSR16
is read/write and can be used to directly manipulate the positions of the read and write pointers
within the circular buffer. Note: in the 1876/1881, CSR16 is read-only and cannot be used to
directly control the positions of the pointers.
July 23, 1998
1881M
5-4
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