Control And Status Register 1 - LeCroy 1881M Manual

Product Description

2.5.2 Control and Status Register 1

The acquisition configuration of the module is primarily defined in CSR1.
a
BYTE 3
0 X X 0 X X X X
31 30 29 28 27 26 25 24
ENABLE INTERNAL TESTER
ENABLE SPARSIFICATION
•
ENABLE SPARSIFICATION : Setting this bit causes data values which are less than the threshold
for the corresponding channels to be discarded during conversion. Only those data values which exceed
their respective thresholds are written to the buffer. CSRC0000000
thresholds for channels 0 - 63 respectively. If this bit is reset (the power up state) the unit will always
readout 64 channels.
•
ENABLE INTERNAL TESTER : This bit must be set for the internal tester to be operative. If set, a
level on UR0 and UR1, normally provided by the 1810 CAT will determine the amplitude of a test
pulse applied to all channels. The test pulse may be software triggered or external but should be
approximately 500ns in duration.
•
FAST CLEAR WINDOW: Bits <27:24> determine the length of time the on-board timer permits the
user to issue a fast clear to the module after the end of acquisition. The fast clear window begins
immediately following the end of the gate . For the on-board FCW to be used the 1810 CAT FCW
must be disabled ( CSR1 <2> = 0 ). Once the fast clear window has ended, the current event is placed
in the multiple event buffer and must either be read out or skipped. When read, the status of the bits is
presented. +
July 23, 1998
1881M
CSR 1 BIT DEFINITIONS
BYTE 2
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
FAST CLEAR WINDOW
0000 2.05us 1000 18.4us
0001 4.10us 1001 20.5us
0010 6.14us 1010 22.5us
0011 8.19us 1011 24.6us
0100 10.2us 1100 26.6us
0101 12.3us 1101 28.7us
110122131072ns
0110 14.3us 1110 30.7us
0111 16.4us 1111 32.8us
524280ns
Figure 2-3 CSR1 Bit Definition
2-6
BYTE 1
* 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
CONVERSION MODE
00 reserved
01 13 bit
10 12 bit
11 reserved
Overrun detect disable
ENABLE FC FROM TR5 (CAT)
ENABLE FCW FROM TR5 (CAT)
ENABLE GATE FROM TR6 (CAT)
ENABLE CIP TO TR7
CSR1 POWER-UP OR MASTER RESET STATE: 0x0000040
- CSRC0000003F
h
BYTE 0
X X 0 X X X X X
7 6 5 4 3 2 1 0
X - USED BITS
* - UNUSED BITS
contain the
h