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1881M
Product Description
2. Product Description
2.1 Introduction
The LeCroy Model 1881M provides 64 channels of analog to digital conversion in the FASTBUS format.
It is designed for elementary particle and nuclear physics experiments and was developed to meet the fast
conversion time needs of modern experiments. Its conversion time is well matched with that of the 1872A,
1876, and 1877 Time to Digital converters for very fast total system throughput. The 1881M is also
compatible with the LeCroy 1810 Calibration and Timing (CAT) module to simplify the implementation
of multiple module systems. The measurement in the 1881M is performed using the MTD133 and the
MQT200S, full custom ASICs developed by LeCroy Corporation.
2.2 General Description
The 1881M Analog to Digital Converter offers all the flexibility of the 1880 series Analog to Digital
converters, but with an approximately 12 µs conversion time for all 64 channels. It has 50 fC least count
with a full 13 bits of dynamic range above pedestal for each channel. Permissible gate widths may vary
from 50 to 500 ns. Each 1881M has 64 channels of front panel input and a single gate input. Events are
stored in an on-board sixty four event cyclic buffer memory. A threshold memory permits the loading of a
separate constant for each channel, which is used to suppress unwanted data. Both front panel control
inputs are differential ECL (dECL) and are terminated by a balanced 102 Ω impedance matching network.
The terminations may be disconnected using jumpers to allow daisy chaining of modules.
Operation of the 1881M can be thought of in four phases: programming, acquisition, conversion, and
readout. Once the control and status registers have been properly programmed, the module is in acquisition
mode and ready to accept a gate pulse. The duration of the gate pulse defines the acquisition phase. The
gate may be provided either via a front panel dECL input, via the 1810 CAT module, or a nominal 500 ns
pulse triggered by a write to CSR0 <7>. For the duration of this gate signal, each of the 64 individual
inputs integrate the charge applied to them. Immediately following this acquisition phase, the data is
converted to a digital representation and then placed in a multi-event buffer to await readout. If
sparsification is selected, data is discarded from channels that are below their individual thresholds. The
data is thus 'sparsified' (also known as zero suppression), so that signals on the front end inputs less than
the programmed threshold values are not buffered. Using this method, it is not necessary to transmit
unwanted data over FASTBUS.
A fast clear may be applied to the module any time from 100ns after the end of the gate until the end of the
Fast Clear Window (FCW). If a fast clear is applied during this period, the event currently being converted
will be discarded. It is important to realize that setting the FCW to longer than 10 µs will increase the
conversion time of the module to FCW + 1us. If an external FCW is selected from the CAT of less than
10µs from the end of the gate, then a FCW will cause an internal FCW of 11 µs with a corresponding
conversion time of 12 us. There is no restriction within the 1881M of the maximum FCW that may be
applied externally. Clears should not be applied outside of the fast clear window.
The data of the 1881M is stored as a 32 bit word, each of which contains charge data, channel number, the
geographic address and a word parity bit. The functionality of the 1881M can be tested using the internal
tester in conjunction with a 1810 CAT module. The module does not provide any trigger outputs.
2-1
July 23, 1998
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