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1881M
Theory of Operation
4.1.6 FASTBUS Control
CSR16 monitors both memory pointers by displaying number of the buffer each pointer references. CSR16
<13:8> is the buffer number for the Read pointer and CSR16 <5:0> is the buffer number for the Write
pointer. The selection of bits aligns the buffer numbers on byte boundaries. CSR16 is a read only register
and is normally the only access to the Read and Write pointers.
Two FASTBUS broadcasts are implemented to facilitate the monitoring of buffering status. The Sparse
Data Scan (Case 3, code 09
) and an 1881M specific broadcast (Case 8, code BDh) causes the 1881M to
h
assert TP if there are any events buffered. This is determined by the relative positions of the pointers. If the
Write pointer is one ahead of the Read pointer (modulo 64), then there are no events buffered and the Read
pointer should not be advanced to the next buffer.
The Load Next Event (LNE) function (CSR0 <10>) advances the Read pointer to the next page and copies
the word count it finds in the header word to CSR5. This makes the next event ready for a block transfer.
The LNE operation can be a broadcast to an entire system, causing all modules to simultaneously move to
the next event. If readout is not required, another LNE may be issued to advance to the next event,
effectively skipping an event.
The 1881M implements a FASTBUS broadcast to allow sparse module readout. The FASTBUS
broadcast CD
causes the 1881M to assert TP if the word count (CSR5) is not equal to one. After LNE,
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this broadcast indicates which modules have data. If TP is not asserted then all the data in the event has
been 'zero' suppressed. A block transfer from this module will return only a header word.
The master reset sets the Read pointer to page 63 (1F80
) and the Write pointer to page zero. This causes
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the first event to be stored in page zero and allows the LNE operation to advance to page zero for the first
block transfer. The Read pointer protects its page from writes by the front end. When the Write pointer
advances around the buffer to the same page as the Read pointer a buffer full condition exists. This
condition is signaled by extending the CIP to prevent additional gates from being accepted. It is the users
responsibility to ensure that GATEs are not issued when CIP is present on any module. This condition
continues until an event is read or skipped (or master reset).
Even though there are 64 pages in the buffer, because the Read pointer protects a page, only 63 consecutive
events can be collected before the Read pointer must be advanced. In a continuous system, where readout
and data collection are interleaved, this protection scheme prevents the page ready for readout from being
corrupted by a new data.
4.1.7 Memory Test Mode
A special Memory Test Mode (MTM is implemented to allow the entire memory to be tested. When this
mode is enabled the Read pointer becomes accessible as the NTA in Data Space (completely separate from
the CSR NTA). All other functions remain the same and the module can be used for data acquisition if the
Data Space NTA is treated carefully.
4.1.8 Re-reading Events
In normal circumstances the data from an event is expected to be read only once. If, for some reason, it is
necessary to re-read the page of memory that has just been read there are two options. It should be noted
that once a LNE has been issued after the block read, the integrity of the data is not guaranteed (as a new
event may have overwritten it). Assuming that a LNE has NOT been issued then in regular operating
mode: Disable the gate, issue 64 LNEs, and then perform a regular block read. Another method is to
Switch to Memory Test Mode by writing to CSR0<6> and read the NTA (the read pointer) from CSR16.
mask the bottom seven bits to zero of CSR16 and perform a random read from this calculated address. The
writing of the data space NTA implicit in this operation is required.. The word read will be the header
word of the event that is to be re-read and it contains the number of data words for that event. Mask all bits
except the bottom six to zero and write to CSR5. Switch back to normal operating mode. Perform block
read normally (do NOT do LNE before block read). The advantage of this technique is that gates need not
be disabled as the normal CIP interlocks will protect against event overwrites.
July 23, 1998
4-2
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