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Related Manuals for LeCroy 1881M
Summary of Contents for LeCroy 1881M
- Page 1 MODEL 1881M 64 CHANNEL FASTBUS ADC...
- Page 2 CAUTION Cooling It is imperative that the module 1881M ADC be well cooled. Be sure fans move sufficient air to maintain exhaust air temperature at less than 50_ C. Installation "Hot" insertion (insertion with crate power turned on) of modules is supported in accordance with the FASTBUS specification.
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Page 4: Table Of Contents
Table of Contents Table of Contents 1............................0-iii 1. General Information......................1-1 1.1 Purpose......................1-1 1.2 Unpacking and Inspection..................1-1 1.3 Warranty......................1-1 1.4 Product Assistance....................1-1 1.5 Maintenance Agreements..................1-1 1.6 Documentation Discrepancies.................1-2 1.7 Software Licensing Agreement................1-2 1.8 Service Procedure....................1-2 2............................1-2 2. Product Description......................2-1 2.1 Introduction......................2-1 2.2 General Description....................2-1 2.3 Specifications......................2-2... - Page 5 Table of Contents 4.1.8 Re-reading Events.................4-2 4.1.9 Readout During Conversion..............4-3 4.1.10 FASTBUS Write to Data Memory............4-3 4.1.11 Fast Clears..................4-3 4.1.12 Internal Tester..................4-3 5. Theory of Operation......................5-1 5.1 General Description of Buffer Architecture..............5-1 5.1.1 Multi-Event Buffer Memory Organization..........5-1 5.1.2 Buffer Memory Pointers................5-1 5.1.3 Buffer Full/Empty Conditions..............5-2 5.2 Acquisition and Buffering..................5-2 5.2.1 Readout of MTDs.................5-4...
- Page 6 Table of Contents List of Figures 2-2. CSR0 Write Bit Definition....................2-4 2-3. CSR1 Bit Definition.......................2-6 2-4. CSR16 Bit Definition......................2-7 2-5. Header word Format......................2-10 5-1. Simplified 1881M Interface/Buffer Block Diagram..............5-1 5-2. 1881M Circular Buffer.....................5-2 July 23, 1998...
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Page 8: General Information
LeCroy are covered by the original equipment manufacturers' warranty only. In exercising this warranty, LeCroy will repair or, at its option, replace any product returned to the Customer Service Department or an authorized service facility within the warranty period, provided that the warrantor's examination discloses that the product is defective due to workmanship or materials and has not been caused by misuse, neglect, accident or abnormal conditions or operations. -
Page 9: Documentation Discrepancies
Products requiring maintenance should be returned to the Customer Service Department or authorized service facility. If under warranty, LeCroy will repair or replace the product at no charge. The purchaser is only responsible for the transportation charges arising from return of the goods to the service facility. For all LeCroy products in need of repair after the warranty period, the customer must provide a Purchase Order Number before any inoperative equipment can be repaired or replaced. -
Page 10: Product Description
13 bits of dynamic range above pedestal for each channel. Permissible gate widths may vary from 50 to 500 ns. Each 1881M has 64 channels of front panel input and a single gate input. Events are stored in an on-board sixty four event cyclic buffer memory. A threshold memory permits the loading of a separate constant for each channel, which is used to suppress unwanted data. -
Page 11: Specifications
LEDs to indicate status. Cables necessary for proper installation can be purchased from LeCroy. See Section 3.1 for more information regarding cabling. 2.4.1 Displays Two colored LEDs exist on the front panel of the 1881M to indicate the status of operations. The LED outputs are pulse stretched for visibility. •... -
Page 12: Outputs
51 Ω resistors in series across the signal at the receiver and connect the center tap via a 0.1 µF capacitor to ground. If LeCroy ECL line products are used to receive the signal the termination is already included internally. Differential ECL cannot be Wire OR’ed. - Page 13 LOAD NEXT EVENT: Advances Read pointer (this is the data space NTA when MTM is set) to first location of next event, then copies word count from header word of that event to CSR5. This makes the 1881M ready for a block transfer to readout one entire event. •...
- Page 14 MTM : Memory test mode allows the direct addressing of the buffer memory using the data space NTA (normally writes to data space NTA are ignored.). When this bit is clear the 1881M acts as a FIFO (First In First Out) from DSR0.
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Page 15: Control And Status Register 1
1881M Product Description 2.5.2 Control and Status Register 1 The acquisition configuration of the module is primarily defined in CSR1. CSR 1 BIT DEFINITIONS BYTE 3 BYTE 2 BYTE 1 BYTE 0 CONVERSION MODE 00 reserved 01 13 bit 10 12 bit... -
Page 16: Control And Status Register 3
2.5.5 Control and Status Register 7 CSR7 is used to specify the broadcast classes to which an 1881M will respond. It is implemented as a 4 bit read/write register. Bits 3 through 0 correspond to broadcast classes 3 through 0 respectively. If bit N is set, the 1881M will be selected by a broadcast to class N devices. -
Page 17: Fastbus Operations
The model 1881M responds to geographical addressing in both CSR space and Data Space. 2.6.1.3 Broadcast Addressing The following is a list of Broadcast operations responded to by the 1881M. The case numbers are from the IEEE 960-1989 FASTBUS specification, Table 4.3.2. Example address use G=0 and L=1 for broadcasts on the local FASTBUS segment only. -
Page 18: Data Space
2.7 Data Space Data memory in the 1881M ADC is a 8K word circular buffer, organized in sixty four pages of 128 words each. Data resulting from an event is stored in one of the sixty four buffers. Each event buffer contains enough locations to hold the maximum data resulting from a single event (65 words). -
Page 19: Header Word Format
2.7.2 Data Word Format The 1881M time data is read out in 32 bit data word. The 13 least significant bits are the charge data and the 6 bits from 17 through 22 are the channel identification. The most significant byte contains the geographic address, parity, and the buffer number (modulo 4). -
Page 20: Readout
2.8.2 Block Transfer Read from Data Space Block transfers are the preferred way to read data from the 1881M, and this is facilitated by the Load Next Event function, CSR0<10>. A write to CSR0<10>, increments the internal read pointer by one and loads CSR5 with the word count for that event. -
Page 21: Example Code
This means that the experimental trigger decision making and the conversion can continue in parallel. Additionally the CIP output signal from the 1881M can be enabled to TR7, so that all 1881M ADCs in a crate could be wire OR'ed to produce a crate wide CIP. This practice is, however, incompatible with the use of TR7 by the 1810 CAT. - Page 22 (ARRAY_SIZE, data); fb_cycle_disconnect(); return(fb_read_length()/4); /* The routine 'test_for_buffer' uses FASTBUS broadcasts to poll for non empty set of buffers in the 1881M. This is a T-pin scan. */ unsigned long test_for_buffer() { unsigned long i; fb_cycle_csr_multi(0x000000BDL); /* Sparse Data Scan*/ fb_cycle_read_word(&i);...
- Page 23 /* The procedure 'sort_n_sum' processes the data from one 1881M buffer. It is assumed that the 1881M generates exactly the same number of words for every event and the sum for each hit is computed. This routine would function for the test modes of the 1881M to compute the mean of the test pulses.
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Page 24: Installation
With either the power on or off, insert the 1881M into one of the slots of the FASTBUS crate. The edge connector of the module should mate with the bus connector with modest pressure. Note the slot number of the module, as it will later be used for addressing. -
Page 25: Input Options
(except for special order) with the links configured for 50 Ω cables and a fixed ground. If it is desired to use 100 Ω differential cabling, it should be noted the 1881M when operated in this mode does not have a true balanced input. Common mode noise should be minimized by reducing ground noise and using shielded twisted pairs. - Page 26 1881M Installation flowing out of the board may be added (using a very large resistor to a negative supply) to cure the non- linearity problem, but this will simply move the pedestals and will not affect the magnitude of the rate shift.
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Page 28: Operating Instructions
128 locations each. Each page can store the data from one event. Two pointers are maintained by the 1881M. The Read pointer is the location of data word to be read by the FASTBUS and the Write pointer is the location for storing the next data word from the front end. These pointers implement a FIFO for events (pages) and for data words. -
Page 29: Fastbus Control
CD causes the 1881M to assert TP if the word count (CSR5) is not equal to one. After LNE, this broadcast indicates which modules have data. If TP is not asserted then all the data in the event has been 'zero' suppressed. -
Page 30: Readout During Conversion
It should also be realized that if any cables are connected to the unit when the charge pulse is issued, the pulse will be shared between the 1881M and the cabling. July 23, 1998... -
Page 32: Theory Of Operation
5.1 General Description of Buffer Architecture The buffer memory on the 1881M is a 8K word SRAM structure with a word width of 32 bits. The memory is constructed out of eight 8K x 8, 12ns SRAM. Access to the buffer memory from the module's front end (i.e. -
Page 33: Buffer Full/Empty Conditions
See section 4.1.1 for further discussion of Load Next Event. 5.2 Acquisition and Buffering The LeCroy Model 1881M ADC use the LeCroy MTD133 and MQT200S to provide a Wilkinson converter with an effective clock rate of 1.6ghz. The MQT200S is a charge to time converter that collects charge during the gate and then issues a pulse whose width is proportional to the charge collected after the gate. - Page 34 IC and TDC products making more general use of its capabilities please contact your local sales representative or the factory. In the 1881M the MTD133 is used as a 8 channel single edge sensitive common start TDC with a 0.6ns resolution.
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Page 35: Readout Of Mtds
Several Control and Status Registers (CSR’s) control the configuration and operation of the 1881M. The following is a list of the CSR’s contained in the 1881M and a brief description of their function(s): CSR0, CSR1 - primary control and configuration registers. These registers contain the configuration bits for all operational modes of the 1881M. -
Page 36: Secondary Addressing In Data Space
CSR5 > (2048 - RPA), then RPA will wrap around back to the beginning of the page. Note: In contrast to MTM in the 1881, since the 1881M NTA appears as only 11 bits, there is no need for the user to keep track of the Read Page to avoid accidentally changing the page to which the FASTBUS Read Pointer is pointing. -
Page 37: Mechanisms For Fastbus Readout
): Assert Tpin on following read cycle if the circular buffer is Empty. 1881M Unique Sparse Data Scan (case 8c, code CD ): Assert Tpin if CSR5 = 1. This scan only has meaning after a Load Next Event command has been executed. It is used to determine if the event just loaded has unsuppressed data words. -
Page 38: Multi-Module Data Transfers (Multi-Block)
The 1881M fully supports the Multi-Module Data Transfer (MDT-1) specification. Assuming a group on 1881M modules has been configured for a MDT scan as per the specification, it must first be established that all modules involved in the scan have data available. This could be done, for example, through a broadcast LNE.
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