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5. Theory of Operation
5.1 General Description of Buffer Architecture
The buffer memory on the 1881M is a 8K word SRAM structure with a word width of 32 bits. The
memory is constructed out of eight 8K x 8, 12ns SRAM. Access to the buffer memory from the module's
front end (i.e. MTD readout) and from FASTBUS is completely interleaved, resulting in a synchronous
dual-ported memory.
Readout of events from the MTDs into the buffer memory can occur at a maximum rate of 20MHz while
readout of the buffer memory to FASTBUS via Block transfers can proceed at a rate up to 10MHz. It is
important to note that front end/FASTBUS access to the memory is synchronous and interleaved 2:1.
This means that the maximum transfer rate to FASTBUS will always be exactly half of the front-end
readout rate which is itself half of the 40MHz system timebase. Additionally, since the FASTBUS
interfacing circuits are operating from the same clock as the memory control circuits, DK and AK response
times are also a function of the 40MHz timebase.
Figure 5-1 shows a simplified block diagram of the 1881M data paths. Event data is readout of the MTDs
through a pipeline at 20MHz into the buffer memory. The pipeline stage is required to achieve proper
synchronism with the memory as well as compute the data word parity. Events are readout to FASTBUS
through a two stage pipeline at up to 10MHz, depending on the speed of the Master. The FASTBUS
readout pipeline stages are required to maintain the maximum transfer rate to the asynchronous FASTBUS.
The addresses for front-end and FASTBUS access are multiplexed at a rate of 40MHz.
1881M ADC Module
FASTBUS
Segment Connector
TTL/ECL register
FAD<31:0>
Fastbus protocol
Figure 5-1 Simplified 1881M Interface/Buffer Block Diagram
5.1.1 Multi-Event Buffer Memory Organization
The 8K memory is logically partitioned into pages, each representing a separate event buffer. For the
1881M, there are 64 pages or buffers, each 128 words long. Since there are a maximum of 64 data words
plus one header word per event, each page of memory can hold one complete event.
5.1.2 Buffer Memory Pointers
The eight individual buffers are logically organized as a circular buffer structure.
maintained into the circular buffer memory - MTD Write Pointer (MWP) and FASTBUS Read Pointer
(FRP). Each pointer is really made up of two separate pointers: a page pointer - Read Page (RP) and Write
Page (WP) - and an address pointer within a that page - Read Page Address (RPA) and Write Page Address
(WPA). See Figure 2. How the buffer pointers are controlled depends on the operational mode of the
module.
1881M
2 Stage Pipeline
32
AD<31:0>
Memory Manager
Fastbus Interface
Address
MTD readout control
40MHz
5-1
Pipeline
32
Circular Buffer
Theory of Operation
MTD Data
MTD's
Two pointers are
July 23, 1998
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