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Product Description
2.3 Specifications
Please refer to the model 1881M technical data sheet for a complete summary of all relevant specifications.
2.4 Front Panel
The LeCroy Module 1881M ADC front panel provides the user with connectors for easy system integration
and LEDs to indicate status. Cables necessary for proper installation can be purchased from LeCroy. See
Section 3.1 for more information regarding cabling.
2.4.1 Displays
Two colored LEDs exist on the front panel of the 1881M to indicate the status of operations. The LED
outputs are pulse stretched for visibility.
•
Slave Addressed LED: As per the FASTBUS specification, this yellow LED is lit whenever the ADC
module is address locked by either direct addressing or a broadcast operation.
•
GATE LED: This green LED is illuminated whenever the ADC registers a gate. The gate may come
via the front panel input marked Gate, from the 1810 CAT module, or from a write to CSR0 <7>.
2.4.2 Inputs
All analog inputs are received via four 34 pin connectors. A 3M connector type 3414-6034 or a LeCroy
connector part number 403 220 034 with pull tab part number 403 910 034 will mate with the ADC header
and provide strain relief. The bottom two pins of each of the four headers are connected to the clean analog
ground within the module. The analog inputs are numbered from top to bottom in ascending order.
•
IN: 64 inputs are used to receive individual channel signals. It is recommended that the source's output
DC impedance exceed 1 KΩ for each of these signals to avoid excessive pedestal spread and degraded
temperature performance. The inputs may be configured in several different modes. These include 50 Ω
single ended, 100 Ω differential, and 100 Ω pseudo-differential. It is important to verify the jumper
links are correctly configured. See Section 3.1.2 for Input options
All front-panel control inputs to the 1881M are differential ECL compatible with the ECLine standard.
Each pair of differential inputs is terminated with an effective 102 Ω . Two control inputs are differentially
received via a 6 pin header located at the bottom of the front panel.
The control signals can be connected by single pair headers AMP part number 5-87456-2. A brief
description of each input follows below:
•
CLR: A dECL input used to issue fast clears to the module. A clear pulse can be issued at any time
during the FCW provided it is at least 100 ns wide. When a clear is issued, the data of the current
event is cleared and the module returns to acquisition mode after a delay equal to the fast clear time
beyond the trailing edge of the pulse. The control and status registers are not affected by a clear. This
signal may also be applied by writing CSR0<31> or from the 1810 CAT via TR0. Note all the clear
sources are simply OR'ed.
•
GATE: A front panel dECL input which receives the gate input pulse. This signal defines the time
during which charge will be integrated on each of the 64 IN inputs. The gate pulse may also be applied
from the 1810 CAT module via TR6 on FASTBUS. The source is selected using CSR1 <1>. The
test gate is generated by a write to CSR0<7>. It is OR'ed with the selected source. It should be
noted that if the selected gate source is high this will cause internal gates not to function.
July 23, 1998
1881M
2-2
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