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Installation
3.1.2 Input options
The 1881M has a number of different input configuration options. These allow both 100 Ω twisted pair
and 50 Ω coaxial cables to be correctly terminated. The options can be selected in the field using pluggable
links. The options available are:
•
Single ended signals on 50 Ω cables, negative polarity, fixed or floating ground.
•
Differential signals on symmetrically terminated twisted-pair cables with nominally 100 Ω line
impedance.
Unlike the 1882/5 units the 1881M cannot be configured for positive inputs. The units are normally
shipped (except for special order) with the links configured for 50 Ω cables and a fixed ground.
If it is desired to use 100 Ω differential cabling, it should be noted the 1881M when operated in this mode
does not have a true balanced input. Common mode noise should be minimized by reducing ground noise
and using shielded twisted pairs. Figure 3-1 illustrates the options available. To select the different
options see the end of this section. The recommended operating mode, and the only one tested during
production testing is 50 Ω single ended.
This node is common to each set of 16 channels
To operate in a truly balanced configuration pulse transformers should be used on the input. In this mode
the 1881M should be configured for single ended 50Ω operation. In this case however, that the AC
coupling thus introduced can cause pedestal shift problems at high input rates. In order to estimate this
effect, it is simply necessary to know the amount of charge flowing into each channel per second. This
figure should be calculated independently of the gate as the transformer is before the gate switch. A
transformer will not couple a DC current so this mean pulse current will be balanced by a DC offset current
in the opposite direction.
For example, consider an experiment with a 10KHz mean rate of pulses of -100pC magnitude (2000 codes)
and a gate width of 500ns. The mean input current is -1 µA, hence there will be a DC offset of +1µA added
to the input current. With a 500ns gate this would correspond to 500fC. This implies that a pedestal shift
of 10 codes will occur between a very low rate and the 10KHz rate calculated. This maybe acceptable,
especially considering the considerable gain in noise immunity. Consider an experiment making extensive
use of the fast clear with a mean rate of 200KHz and again a 500ns gate. The shift then becomes 200 codes,
a considerably greater problem. In addition, the offset current should be kept as small as possible (certainly
less than +50uA) to avoid deterioration of the integral non-linearity. If necessary a balancing current
July 23, 1998
1881M
J2/4
51.1
51.1
This diagram is intended to show how the link
settings select input options. It is not intended to
show circuit function
Figure 3-1 Input Circuit
3-2
J5
1.00K
20uF
Pin 33
Pin 34
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