Readout During Conversion; Fastbus Write To Data Memory; Fast Clears; Internal Tester - LeCroy 1881M Manual

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1881M

Theory of Operation

4.1.9 Readout During Conversion

Readout during conversion is supported by the 1881M, no significant penalty in either conversion time or

FASTBUS performance will result. The only concern is that of increased front end noise. Some increased

noise is inevitable (approximately an additional 0.3 codes). The quality of the analog connections between

the experiment and the 1881M will obviously have a major impact on the rejection of noise sources,

including FASTBUS activity. The most significant cause of noise (picked up externally by cabling) is

allowing FASTBUS activity during gates. For most experiments (if not too difficult to achieve) preventing

FASTBUS activity during gates (e.g. using FASTBUS WT) will give improved noise performance. The

performance impact is obviously negligible as the gate is less than 500ns wide.

Although not pertinent to data acquisition, it is possible to write to the data memory via FASTBUS. This

may be desired for testing. For this purpose, the data memory appears as a 8192 x 32 bit word RAM. Data

may be written into this RAM using random, or broadcast modes. Block writes to data space are not

supported. Since the 1881M event manager is not managing this loading, however, the parity checking,

channel identification, and geographic address identification normally present in the data are not present

when read back.

A fast clear can be applied any time during the fast clear window. This will cause the event just recorded in

the front end not to be buffered. The write pointer for the buffer will not be incremented. The buffering

situation will be as though the cleared event never took place. This action requires 1 usec. before the

module is ready to accept another event (settled to 1 LSB). Fast clears can be applied either from the front

panel input, by writing CSR0 <31> (not a normal operation as it must be timed to occur before the end of

FCW), by using a broadcast write, or via a model 1810 CAT(TR0).

An internal tester has been implemented on board the module 1881M ADC for testing purposes. An

external voltage must be provided between UR1 and UR0. A test pulse proportional to the voltage will be

injected into all 64 channels on the receipt of the leading edge of the gate. This mode is selected by setting

CSR1 <29>. In addition a 500 ns gate can be generated internally by writing a 1 to CSR0 <7>. This test

feature is not intended as a calibration aid. It should also be realized that if any cables are connected to the

unit when the charge pulse is issued, the pulse will be shared between the 1881M and the cabling.

4-3

July 23, 1998

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