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Product Description
TR5 - Fast Clear Window (MPI)
UR0: clean ground from 1810 CAT. Used as relative ground for UR1.
UR1: DC reference level used by internal tester to set amplitude of test pulses. This is typically
generated by the 1810 CAT. The full scale is +10V.
The Fast Clear Window corresponds to the 1810 CAT MPI signal, which can be either programmed
internal to the 1810 or supplied via the 1810 front panel. The Common signal corresponds to the 1810
CAT input signal marked ADC Stop. The Test Pulse input corresponds to the 1810 CAT Test Pulse
output. It should be noted that we refer to the signal as FCW rather than MPI for a good reason. MPI on
the older 1882/5 ADC's caused conversion to be held up while a trigger decision was made. The 1881M
fast clear window does not hold up conversion but rather defines the time up to when an abort can take
place. This means that the experimental trigger decision making and the conversion can continue in
parallel.
Additionally the CIP output signal from the 1881M can be enabled to TR7, so that all 1881M ADCs in a
crate could be wire OR'ed to produce a crate wide CIP. This practice is, however, incompatible with the
use of TR7 by the 1810 CAT. The 1810 uses TR7 to distribute a reference timing signal to 1879 ADC
modules. If a 1810 CAT is in the crate, the 1881M CSR1<0> must be set to zero.

2.12 Example Code

/* The following are examples of some possible general purpose 1881M subroutines. This code has been compiled but never
executed. It is intended only to illustrate the methods. */
/* Include these header files for C applications. */
include <stdlib.h>
/* Program Parameters */
define ARRAY_SIZE 64 /* 8 ics * 8 channels * 1 hits =64 */
define NO_OF_CHAN 64
define SLOT 0x00000000BL
/* FASTBUS Prototypes; Primitive FASTBUS Action Routines */
int fb_cycle_pa_csr(unsigned long slot);
int fb_cycle_pa_data(unsigned long slot);
int fb_cycle_write_word(unsigned long data);
int fb_cycle_read_block(int max_words, unsigned long data[]);
int fb_cycle_read_word(unsigned long * data);
int fb_read_length();
/* Prototypes */
void master_reset(unsigned long slot);
void setup(unsigned long slot);
unsigned long test_for_buffer();
void skip_event();
int read_event( unsigned long data[], unsigned long slot);
void sort_n_sum( long summed_data[]);
/* Routines */
/* The routine 'master_reset' clears the 1881M, all is set to the power up
July 23, 1998
1881M
2-12

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