Outputs; Control And Status Registers - LeCroy 1881M Manual

2.4.3 Outputs

The front panel CIP (Conversion in Progress) output from the 1881M is differential ECL compatible with
the ECLine standard. Each of differential outputs is pulled down with 300 Ω to -5.2 V. If the CIP signal is
used, it should be terminated at the receiving end in 100 Ω . The best method of doing this is to connect
two 51 Ω resistors in series across the signal at the receiver and connect the center tap via a 0.1 µF
capacitor to ground. If LeCroy ECL line products are used to receive the signal the termination is already
included internally. Differential ECL cannot be Wire OR'ed.
•
CIP: Conversion in Progress (CIP) is a single dECL signal provided to aid in the gating logic. While
CIP is true, the unit is not capable of accepting a new gate. It should be noted that if an extended
FCW is used this will delay the end of CIP. It is the users responsibility to ensure that GATEs are
NOT issued during CIP.

2.5 Control and Status Registers

Seventy control and status registers (CSR) are implemented in the 1881M: CSR0, CSR1, CSR3, CSR5,
CSR7, CSR16, and CSRC0000000
2.5.1 Control and Status Register 0
Functions necessary even for the simplest of operations are contained in CSR0. In order to implement these
functions most economically, the definition of the bits for CSR0 are not the same for Read and Write
operations. Some bits are inherently meaningful only for write operations, because their status can only be
altered by writing to another bit in the register. Other bits, such as the module identification bits, are only
meaningful for read operations. When read, the 1881M presents 104F
as its manufacturer's identification. CSR0 is the default register when a primary address to control space is
issued. See section 2.6.1 for more information regarding addressing. See Figures 2-1 and 2-2 for individual
bit definitions.
BYTE 3
0 0 0 1 0 0 0 0
31 30 29 28 27 26 25 24
1881M
- C000003F .
h h
CSR 0 READ BIT DEFINITIONS
BYTE 2
0 1 0 0 1 1 1 1
23 22 21 20 19 18 17 16
MULTIBLOCK CONFIGURATION
00 - BYPASS
01 - PRIMARY LINK
10 - END LINK
11 - MIDDLE LINK
MEMORY TEST MODE ENABLED
LOGICAL ADDRESSING ENABLED
1881M MODULE IDENTIFICATION - 104F
Figure 2-1 CSR0 Read Bit Definition
2-3
on the Address/Data bus lines 16-31
h
BYTE 1
0 0 0 X X 0 0 X
15 14 13 12 11 10 9 8
CSR0 POWER-UP OR MASTER RESET STATE: 0x104F0000
Product Description
BYTE 0
0 X 0 0 0 0 X 0
7 6 5 4 3 2 1 0
X - USED BITS
* - UNUSED BITS
July 23, 1998