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Product Description
2.5.7 Control and Status Register C000000
These 64 read/write registers are used to program the threshold settings for each of the input channels. If
during buffering a given channel's data value is less than its threshold setting, that data will not be buffered.
The threshold is NOT subtracted from the data written into the buffer. The threshold value RAM is 13 bits
wide and is accessed via the low 13 bits of CSRC0000000h- C0000003Fh. The upper 16 bits will be
ignored on write and always read back as zero. These CSR's are NOT cleared by power-up or Master
Reset. Setting bits 12 and 13 of a threshold will disable the channel completely
2.6 FASTBUS Operations
2.6.1 FASTBUS Address cycle
The 1881M ADC responds to geographical, logical and broadcast addressing.
2.6.1.1 Logical Addressing
CSR3<31:16 > contain the logical address to which the 1881M will respond in both CSR Space and Data
Space.
2.6.1.2 Geographic Addressing
The model 1881M responds to geographical addressing in both CSR space and Data Space.
2.6.1.3 Broadcast Addressing
The following is a list of Broadcast operations responded to by the 1881M. The case numbers are from the
IEEE 960-1989 FASTBUS specification, Table 4.3.2. Example address use G=0 and L=1 for broadcasts
on the local FASTBUS segment only.
•
Case 1: General Broadcast. 00000001
•
Case 2: 00000005
•
Case 3: Sparse Data Scan : 00000009
cycle if data present.
•
Case 3a: Sparse Data Scan: 00000019
data or are available for use.
•
Case 4: 0000000D. Devices respond by asserting T-Pin during following read cycle.
•
Case 8-B: 000000BD
•
Case 8-C: 000000CD
unsuppressed data is present in the next buffer.
CSR7<3:0 > controls the classes of class N broadcast to which the 1881M will respond in both Data and
CSR Spaces.
Important note: In some rare cases, the module will not be able to respond to a broadcast primary address
cycle within the 500nsec minimum Master/ANC Logic handshake time. In these circumstances, the
module will assert the Fastbus WAIT signal for the period of time required by the slave to properly decode
the broadcast.
July 23, 1998
1881M
. All devices respond to subsequent data cycles.
h
. Only devices of class N respond to subsequent data cycles.
h
Devices respond by asserting T-Pin during following read
h
. Devices respond by asserting T-Pin if they contain no
h
. Identical to the case 3 scan above except it is specific to LeCroy ADC's.
h
. 1881M ADCs respond by asserting T-Pin during following read cycle if
h
2-8
- C000003F
h
h
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