Buffer Full/Empty Conditions; Acquisition And Buffering - LeCroy 1881M Manual

Theory of Operation
FASTBUS Read Pointer (FRP): The Read Page (RP) can be manipulated directly by writing to
CSR16. RP may also be effected through the use of the Load Next Event (LNE) command which
prepares the module for FASTBUS readout.
incrementing RP so that the FRP is advanced to the next buffer in the circular structure. In the
default mode of the module, the Read Page Address (RPA) is not accessible to the user. In
Memory Test Mode, the RPA becomes the Data Space Next Transfer Address and may also serve
as a write pointer to Data Space. See section 4.1.7 for discussion of Memory Test Mode.
MTD Write Pointer (MWP): The Write Page (WP) can be manipulated directly by the user by
writing to CSR16. Otherwise, WP is maintained by the front-end MTD readout circuits. The
Write Page Address (WPA) is maintained solely by the front-end MTD readout circuits and is not
accessible to the user in any way.
Fastbus Read Pointer (FRP)
12 11 10 9 8 7 6 5 4 3 2 1 0
Read Page (RP)
Read Page Address (RPA)

5.1.3 Buffer Full/Empty Conditions

Upon power up of the module or Master Reset via FASTBUS command, the MTD Write Pointer is
pointing to the beginning of buffer zero and the FASTBUS Read Pointer is pointing to the beginning of
buffer sixty three. See figure 5-2. This relative positioning of the pointers, that is the read pointer one
buffer behind the write pointer, defines the Empty Condition. Conversely, the Full Condition is defined at
the case where the write pointer is one buffer behind the read pointer. The Full and Empty conditions as
described apply before a LNE is issued: i.e. if a single event is in the buffer and a LNE is issued, the Empty
condition would be true even though an event is now ready for readout.
As events are readout of the MTDs into the circular buffer, the WP is incremented to point to the next
available buffer. Similarly, as events are prepared for readout via FASTBUS using the Load Next Event
(LNE) command, RP is incremented to point to the next event which will be read out of the circular buffer.
For example, after one event has been completely buffered (after power-up or reset) WP would be at buffer
one and WPA would be zero. RP would be at buffer sixty three and RPA would be zero. A subsequent
Load Next Event would prepare the module for FASTBUS readout of that event by incrementing RP to
buffer zero. See section 4.1.1 for further discussion of Load Next Event.

5.2 Acquisition and Buffering

The LeCroy Model 1881M ADC use the LeCroy MTD133 and MQT200S to provide a Wilkinson
converter with an effective clock rate of 1.6ghz. The MQT200S is a charge to time converter that collects
charge during the gate and then issues a pulse whose width is proportional to the charge collected after the
gate. The MTD133 is an eight channel Time to Digital Converter (TDC) implemented as a full custom
CMOS ASIC. It combines a 400 MHz counter with a silicon delay line based interpolator. 64 individual
MQT200S charge to time converters are used. The MQT200S has a very low virtual ground input
impedance. By configuring resistors using pluggable links, the input can be configured as a 50 Ω single
ended or 100 Ω differential (not fully balanced) input.
The gate is provided externally, either from a 1810 CAT or the front panel, and determines the charge
collection time. Immediately after the gate the clear is removed from the storage capacitor (by turning off a
July 23, 1998
1881M
A LNE command would have the effect of
12 11 10 9 8 7 6 5 4 3 2 1 0
63
0
1
62
61 2
60 3
Figure 5-2 1881M Circular Buffer
5-2
MTD Write Pointer (MWP)
Write Page (WP) Write Page Address (WPA)